A low power radix-2 FFT accelerator for FPGA

Jiménez-Fernández

IEEE Trans. Biomed. Circuits Syst.

et al. 2018

137

Auscultation is one of the most used techniques for detecting cardiovascular diseases, which is one of the main causes of death in the world. Heart murmurs are the most common abnormal finding when a patient visits the physician for auscultation. These heart sounds can either be innocent, which are harmless, or abnormal, which may be a sign of a more serious heart condition. However, the accuracy rate of primary care physicians and expert cardiologists when auscultating is not good enough to avoid most of both type-I (healthy patients are sent for echocardiogram) and type-II (pathological patients are sent home without medication or treatment) errors made. In this paper, the authors present a novel convolutional neural network based tool for classifying between healthy people and pathological patients using a neuromorphic auditory sensor for FPGA that is able to decompose the audio into frequency bands in real time. For this purpose, different networks have been trained with the heart murmur information contained in heart sound recordings obtained from nine different heart sound databases sourced from multiple research groups. These samples are segmented and preprocessed using the neuromorphic auditory sensor to decompose their audio information into frequency bands and, after that, sonogram images with the same size are generated. These images have been used to train and test different convolutional neural network architectures. The best results have been obtained with a modified version of the AlexNet model, achieving 97% accuracy (specificity: 95.12%, sensitivity: 93.20%, PhysioNet/CinC Challenge 2016 score: 0.9416). This tool could aid cardiologists and primary care physicians in the auscultation process, improving the decision making task and reducing type-I and type-II errors.

Section: Discussionmentioning

confidence: 99%

Deep Neural Networks for the Recognition and Classification of Heart Murmurs Using Neuromorphic Auditory Sensors

Jiménez-Fernández

IEEE Trans. Biomed. Circuits Syst.

et al. 2018

137

Proceedings of the 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation

“…Hundreds of research implementations [22,56] and commercial implementations [1,[3][4][5][6]22] of FFT accelerators exist intended both as stand-alone accelerators, and to be integrated in larger accelerators [125]. Work on supporting FFT acceleration exists for FPGAs [94], GPUs [84] and specialized architectures from linear algebra cores [104] to CGRAs [67,85], machine-learning accelerators [50,80,117], optical computers [78] and sonic computers [103].…”

Section: Fft Acceleratorsmentioning

confidence: 99%

Bind the gap: compiling real software to hardware FFT accelerators

Woodruff

Armengol-Estapé

Ainsworth

et al. 2022

Specialized hardware accelerators continue to be a source of performance improvement. However, such specialization comes at a programming price. The fundamental issue is that of a mismatch between the diversity of user code and the functionality of fixed hardware, limiting its wider uptake.Here we focus on a particular set of accelerators: those for Fast Fourier Transforms. We present FACC (Fourier ACcelerator Compiler), a novel approach to automatically map legacy code to Fourier Transform accelerators. It automatically generates drop-in replacement adapters using Input-Output (IO)-based program synthesis that bridge the gap between user code and accelerators. We apply FACC to unmodified GitHub C programs of varying complexity and compare against two existing approaches. We target FACC to a high-performance library, FFTW, and two hardware accelerators, the NXP PowerQuad and the Analog Devices FFTA, and demonstrate mean speedups of 9x, 17x and 27x respectively.

IEEE Trans. Emerg. Topics Comput.

“…HE multiply-and-accumulate unit (MAC) implements the equation Y=A×B+C and has a central role in several applications, including image and audio processing [1], [2], convolutional neural networks, and adaptive filtering [3]- [5]. This calls for optimized MAC implementations with reduced power and area.…”

Section: Introductionmentioning

confidence: 99%

Approximate MAC Unit Using Static Segmentation

Di Meo,

Saggese,

Strollo

et al. 2024

In this paper we investigate a novel approximate multiply-and-accumulate (MAC) unit, that computes Y=A×B+C using static segmentation. The proposed architecture uses a unique carry-propagate adder and performs segmentation on the three operands A, B, and C, to reduce hardware cost. The circuit can be configured at design-time by two parameters. The first one controls the segmentation on A and B, while the second one controls the segmentation on C and the adder length. An error compensation technique is also employed, to reduce the approximation error. Error analysis and implementation results in 28nm CMOS for 8-bits multiplier with 20-bits and 24-bits addition are presented. The proposed approximate MACs outperform the state of the art, showing the largest power saving when the mean relative error distance (MRED) is larger than 2×10 −3 and 4×10 -5 for 20 and 24-bits addition, respectively. For MRED of about 6×10 −3 the proposed approximate MAC with 20-bits addition exhibits a power reduction larger than 60% compared to the exact MAC and larger than 27% compared to the state-of-the-art approximate MACs. Application examples to image filtering and template matching show that proposed approximate circuits are good candidates in applications where their error performances are acceptable.