A Low-Power RRAM Memory Block for Embedded, Multi-Level Weight and Bias Storage in Artificial Neural Networks

Pechmann, Stefan; Mai, Timo; Potschka, Julian; Reiser, Daniel; Reichel, Peter; Breiling, Marco; Reichenbach, Marc; Hagelauer, Amelie

doi:10.3390/mi12111277

Cited by 5 publications

(3 citation statements)

References 21 publications

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“…The high-density integration on the chip allows for the ReRAM cells to be closely attached to digital computation units, which decreases energy consumption by avoiding long data paths on the chip. The use of ReRAM technology yielded a 95% reduction in energy consumption for the classification of bio-signals for atrial fibrillation compared to a traditional approach (Pechmann et al, 2021 ). Therefore, ReRAM technology is a promising candidate for realization of personalized gait neuroprostheses relying on artificial neural networks in digital (e.g., as ReRAM storage for weights) and analog in-memory processing (e.g., as an in-memory processing element itself).…”

Section: Interface With the Embedded Computer Architecturementioning

confidence: 99%

Adaptation Strategies for Personalized Gait Neuroprosthetics

et al. 2021

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Personalization of gait neuroprosthetics is paramount to ensure their efficacy for users, who experience severe limitations in mobility without an assistive device. Our goal is to develop assistive devices that collaborate with and are tailored to their users, while allowing them to use as much of their existing capabilities as possible. Currently, personalization of devices is challenging, and technological advances are required to achieve this goal. Therefore, this paper presents an overview of challenges and research directions regarding an interface with the peripheral nervous system, an interface with the central nervous system, and the requirements of interface computing architectures. The interface should be modular and adaptable, such that it can provide assistance where it is needed. Novel data processing technology should be developed to allow for real-time processing while accounting for signal variations in the human. Personalized biomechanical models and simulation techniques should be developed to predict assisted walking motions and interactions between the user and the device. Furthermore, the advantages of interfacing with both the brain and the spinal cord or the periphery should be further explored. Technological advances of interface computing architecture should focus on learning on the chip to achieve further personalization. Furthermore, energy consumption should be low to allow for longer use of the neuroprosthesis. In-memory processing combined with resistive random access memory is a promising technology for both. This paper discusses the aforementioned aspects to highlight new directions for future research in gait neuroprosthetics.

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Section: Interface With the Embedded Computer Architecturementioning

confidence: 99%

Adaptation Strategies for Personalized Gait Neuroprosthetics

et al. 2021

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“…However, the use of more states is also possible. The design of this RRAM memory block has been optimized specifically for use in low-power accelerators for NNs [29].…”

Section: Non-volatile On-chip Rrammentioning

confidence: 99%

A Framework for Ultra Low-Power Hardware Accelerators Using NNs for Embedded Time Series Classification

Reiser

Reichel

Pechmann

et al. 2021

JLPEA

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In embedded applications that use neural networks (NNs) for classification tasks, it is important to not only minimize the power consumption of the NN calculation, but of the whole system. Optimization approaches for individual parts exist, such as quantization of the NN or analog calculation of arithmetic operations. However, there is no holistic approach for a complete embedded system design that is generic enough in the design process to be used for different applications, but specific in the hardware implementation to waste no energy for a given application. Therefore, we present a novel framework that allows an end-to-end ASIC implementation of a low-power hardware for time series classification using NNs. This includes a neural architecture search (NAS), which optimizes the NN configuration for accuracy and energy efficiency at the same time. This optimization targets a custom designed hardware architecture that is derived from the key properties of time series classification tasks. Additionally, a hardware generation tool is used that creates a complete system from the definition of the NN. This system uses local multi-level RRAM memory as weight and bias storage to avoid external memory access. Exploiting the non-volatility of these devices, such a system can use a power-down mode to save significant energy during the data acquisition process. Detection of atrial fibrillation (AFib) in electrocardiogram (ECG) data is used as an example for evaluation of the framework. It is shown that a reduction of more than 95% of the energy consumption compared to state-of-the-art solutions is achieved.

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“…The operation results in a two-element output current vector represented by I 1 and I 2 . Recently, the research community has intensively studied and optimized the performance of the RRAM technology within in-memory MAC-based systems/circuits, specially in simulation environments for early-stage design exploration [13], [14], [15], [16]. Among others, Mehonic et al [17] reported hand-written digit recognition with up to 97% accuracy ratio using an RRAM-based ANN.…”

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confidence: 99%

Experimental Assessment of Multilevel RRAM-Based Vector-Matrix Multiplication Operations for In-Memory Computing

Quesada

Mahadevaiah

Rizzi

et al. 2023

IEEE Trans. Electron Devices

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Resistive random access memory (RRAM)based hardware accelerators are playing an important role in the implementation of in-memory computing (IMC) systems for artificial intelligence applications. The latter heavily rely on vector-matrix multiplication (VMM) operations that can be efficiently boosted by RRAM devices. However, the stochastic nature of the RRAM technology is still challenging real hardware implementations. To study the accuracy degradation of consecutive VMM operations, in this work we programed two RRAM subarrays composed of 8 × 8 one-transistor-one-resistor (1T1R) cells following two different distributions of conductive levels. We analyze their robustness against 1000 identical consecutive VMM operations and monitor the inherent devices' nonidealities along the test. We finally quantize the accuracy loss of the operations in the digital domain and consider the trade-offs between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities for future implementation of IMC hardware systems.

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A Low-Power RRAM Memory Block for Embedded, Multi-Level Weight and Bias Storage in Artificial Neural Networks

Cited by 5 publications

References 21 publications

Adaptation Strategies for Personalized Gait Neuroprosthetics

Adaptation Strategies for Personalized Gait Neuroprosthetics

A Framework for Ultra Low-Power Hardware Accelerators Using NNs for Embedded Time Series Classification

Experimental Assessment of Multilevel RRAM-Based Vector-Matrix Multiplication Operations for In-Memory Computing

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