A Low Power, Small Area Cyclic Time-to-Digital Converter in All-Digital PLL for DVB-S2 Application

Abstract

Abstract-In this paper, a low power, small area cyclic time-to-digital converter in All-Digital PLL for DVB-S2 application is presented. Coarse and fine TDC stages in the two-step TDC are shared to reduce the area and the current consumption maintaining the resolution since the area of the TDC is dominant in the ADPLL. It is implemented in a 0.13 µm CMOS process with a die area of 0.12 mm 2 . The power consumption is 2.4 mW at a 1.2 V supply voltage. Furthermore, the resolution and input frequency of the TDC are 5 ps and 25 MHz, respectively.

The Design of a 0.15 ps High Resolution Time-to-Digital Converter

“…The proposed HR-TDC could realize high resolution with at a low cost. The time resolution of the proposed TDC is 8 times higher than other works published previously [2][3][4][5][6]9]. Also the results are verified by many repetitive measurements.…”

“…9(b) [5] was high, the MUX #1 outputs the STOPD [5] and START [5] and the MUX #2 outputs the STOPD [6] and START [6]. This architecture reduces the number of the time amplifiers from n to 2.…”

“…The proposed HR-TDC using the coarse-fine architecture and the 2S-VTA showed very high resolution with the value of 0.15 ps, which is proper for a high data rate communication system. The gain of a conventional TA was low and not enough for a high-resolution TDC [4,6], whereas the gain of the proposed 2S-VTA is larger than 64, through use of a multi-stage structure. In a conventional TDC, the many TA's are used at every stage of a delay line in a coarse block [4], however we used only two TAs to reduce the area of the TDC.…”

A High-Speed Fully Digital Phase-Synchronizer Implemented in a Field Programmable Gate Array Device

“…Similar solutions concern using a DLL loop to stabilize the delay line parameters against temperature or power supply voltage variations [21]. The known concept of applying a PLL to the CPUCoprocessor synchronization [22] remains also valid in constructing various types of precise TDC systems [23] to guarantee a high synchronization level between the internal signals and appropriate functional blocks of the system. In modern FPGAs it can be achieved e.g.…”