A low power soft error suppression technique for dynamic logic

Kumar, Jayanand Asok; Tahoori, Mehdi B.

doi:10.1109/dftvs.2005.9

Cited by 12 publications

(8 citation statements)

References 13 publications

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“…This is not of serious concern because such transients cannot propagate to the subsequent dynamic gates that are being precharged [9]. However, if the SET pulse width is too long and the hit node is not able to fully recover before the evaluation phase starts, the negative transient may get latched as a static error.…”

Section: Precharge Phase -N Hitmentioning

confidence: 99%

“…However, the area cost of these approaches is at least 2× compared to that of the traditional keeper-based dynamic logic circuit [15]. By adding extra isolation devices, the logic circuit demonstrates better single event resilience [9]. Radiation experimental results show that the cross-section of this approach is~50 % lower than that of the keeper-based design [15].…”

Section: Introductionmentioning

confidence: 99%

“…Radiation experimental results show that the cross-section of this approach is~50 % lower than that of the keeper-based design [15]. However, to achieve better suppression, large area overhead has to be introduced [9].…”

Section: Introductionmentioning

confidence: 99%

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Single Event Resilient Dynamic Logic Designs

Wang

Chen

et al. 2014

J Electron Test

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Dynamic logic families are commonly used in high speed applications, but they are susceptible to single event errors. This paper presents and evaluates three techniques of hardening dynamic logic-layout manipulation using charge sharing, addition of a feedback capacitor across the static inverter, and dual-rail domino logic with differential keepers. The layout-based design has better single event tolerance by sharing charge between NFET devices of the dynamic and static inverters; the design with a feedback capacitor makes the keeper more effective in recovering the hit node because of the increased propagation delay; the differential-keeper structure shows superior SET performance because the hit node could recover through the restoring path in the case of charge loss. These proposed designs along with the reference traditional keeper-based design were fabricated in a 130 nm technology node as shift register chains and then irradiated by heavy ion particles. Experimental results verified the mechanisms and effectiveness of these proposed designs.

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Section: Precharge Phase -N Hitmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Single Event Resilient Dynamic Logic Designs

Wang

Chen

et al. 2014

J Electron Test

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“…To tolerate soft errors occurring on latches, the following methods were proposed: Dual Interlocked storage Cell (DICE) [6], soft error hardened latch scheme [7], Delay-Assignment-Variation (DAV) based optimization method [8], and methods using C-elements [9], [10]. Meanwhile, for soft errors occurring on combina- tional parts, the following error tolerant methods have been proposed: methods using time redundancy [11]- [16], ones using pass transistors [17] and ones using Schmitt triggers [18]. In [10], constructions of soft-error-tolerant FFs capable of correcting soft errors occurring on latches as well as those on combinational parts has been proposed.…”

Section: Introductionmentioning

confidence: 99%

Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability

Ruan

Namba

Ito

2009

IEICE Trans. Inf. & Syst.

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“…Based on this viewpoint, many soft error tolerant methods [7][8][9][10] and soft error analysis methods [11] for soft errors occurring on combinational parts of logic circuits were proposed. In [7], time redundancy method is proposed by Nicolaidis.…”

Section: Introductionmentioning

confidence: 99%

Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit

Sasaki

Namba

Ito

2006

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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In recent high-density and low-power VLSIs, soft errors occurring on not only memory systems and the latches of logic circuits but also the combinational parts of logic circuits seriously affect the operation of systems. The conventional soft error tolerant methods for soft errors on the combinational parts do not provide enough high soft error tolerant capability with small performance penalty. This paper proposes a class of soft error masking circuits by using a Schmitt trigger circuit and pass transistors. The paper also presents construction of soft error masking latches (SEM-Latches) capable of masking transient pulses occurring on combinational circuits. Moreover, experimental results show that the proposed method has higher soft error tolerant capability than the existing methods. For driving voltage VDD=3.3V, the proposed method is capable of masking transient pulses of magnitude 4.0V or less.

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A low power soft error suppression technique for dynamic logic

Cited by 12 publications

References 13 publications

Single Event Resilient Dynamic Logic Designs

Single Event Resilient Dynamic Logic Designs

Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability

Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit

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