Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit

Sasaki, Yui; Namba, Kazuteru; Ito, Hideo

doi:10.1109/dft.2006.60

Cited by 60 publications

(25 citation statements)

References 9 publications

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“…For instance, this approach is adopted by the latches in [19,20,21,18,22,23]. In particular, the robustness of [19,20,21,18] derives from the idea of either splitting the internal nodes and adopting proper feedback structures, or using a Schmitt trigger-like scheme. Instead, solutions in [22,23] improve the latch robustness by inserting either explicit capacitances, or transistors acting as filters for voltage glitches.…”

Section: Introductionmentioning

confidence: 99%

High-Performance Robust Latches

Omaña

Rossi

Metra

2010

IEEE Trans. Comput.

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obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The WestminsterResearch online digital archive at the University of Westminster aims to make the research output of the University available to a wider audience. Copyright and Moral Rights remain with the authors and/or copyright owners.Whilst further distribution of specific materials from within this archive is forbidden, you may freely distribute the URL of WestminsterResearch: ((http://westminsterresearch.wmin.ac.uk/). Abstract-First a new high performance robust latch (referred to as HiPeR latch) is presented, that is insensitive to transient faults affecting its internal and output nodes by design, independently of the size of its transistors. Then, a modified version of the HiPeR latch (referred as HiPeR-CG) is proposed, that is suitable to be used together with clock gating. Both proposed latches are faster than the latches most recently presented in the literature, while providing better or comparable robustness to transient faults, at comparable or lower costs in terms of area and power, respectively. Therefore, thanks to the good tradeoffs in terms of performance, robustness and cost, our proposed latches are particularly suitable to be adopted on critical paths.

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Section: Introductionmentioning

confidence: 99%

High-Performance Robust Latches

Omaña

Rossi

Metra

2010

IEEE Trans. Comput.

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“…Among sequential elements, latch is the most fragile element to soft error since its latching window is much longer than other register elements [8]. Recently, there are many soft error mitigation latch designs have been proposed [4,5,6,7,8,9]. These designs can be classified into the node strengthen type and the soft-error isolation type.…”

Section: Introductionmentioning

confidence: 99%

Robust C-element design for soft-error mitigation

Wey

Peng

et al. 2015

IEICE Electron. Express

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C-element is a widely used component in soft-error tolerant designs to construct a robust soft-tolerant mechanism; however, C-element itself is not a robust device. In this paper, we proposed a robust C-element design by employing two transistors operating in saturation region parallel connected with C-element upper pMOS and lower nMOS to enhance its softerror tolerance. By utilizing the proposed C-element in the prior-art isolated latch designs, the maximum soft error tolerance can be improved by 25.87% as compared with conventional C-element.

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“…Also proposed is a low pass filter using a C-element [24], but it uses a flipflop, and this introduces new vulnerability situations. Other approaches take advantage of the hysteresis property in a Schmitt Trigger to mask transient errors at its internal nodes [25]. Furthermore, transistor folding is used to divide the strike node into many other nodes [14], according to the number of parallel transistor segments used in the folding.…”

Section: Introductionmentioning

confidence: 99%

SET and noise fault tolerant circuit design techniques: Application to 7nm FinFET

Calomarde

Amat

Moll

et al. 2014

Microelectronics Reliability

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Abstract-In the near future of high component density and low-power technologies, soft errors occurring not only in memory systems and latches but also in the combinational parts of logic circuits will seriously affect the reliable operation of integrated circuits. In this paper, we present a novel design style that reduces the impact of radiation-induced single event transients (SET) on logic circuits, and enhances the robustness in noisy environments. This technology's independent design style achieves SET mitigation and noise immunity by strengthening the sensitive nodes using a technique similar to feedback. We propose two alternatives for this methodology in 7nm FinFET, and, to check the accuracy of our proposal, we compare them with previous techniques for hardening radiation at the transistor level against a Single Event Transient. Simulation results show that the proposed method has a higher soft error tolerance capability than existing methods as well as better noisy immunity.

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Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit

Cited by 60 publications

References 9 publications

High-Performance Robust Latches

High-Performance Robust Latches

Robust C-element design for soft-error mitigation

SET and noise fault tolerant circuit design techniques: Application to 7nm FinFET

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