In this work, we analyze the suitability to implement embedded DRAM (eDRAM) cells on FinFET technology and we compare it to classical planar MOSFETs. The results show a significant improvement in the overall cell performance for multi-gate devices. While pMOS FinFET-based memories present better cell behavior and variability robustness, n/pMOS mixed cells show the highest working frequency and a negligible impact on degradation. Finally, we show that using a multiple fin-height strategy, we can reduce (>10%) the layout area of the eDRAM cells.

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The research leading to these results has been supported by the Spanish Ministry of Economy (MINECO) and ERDF funds through project TEC2016-75151-C3-R. (TOGETHER).

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The concept worked in this paper named Turtle Logic (TL) is a probabilistic logic method based on port redundancy and complementary data, oriented to emerging CMOS technologies and beyond, where the thermal noise could be predominant and the reliability of the future circuits will be limited. The TL is a technology independent method, which aims to improve tolerance to errors due to noise in single gates, logic and functional units. The TL operation is based on the consistency relation of redundant inputs. In case of discrepancy, the output of the system keeps the previous value. Therefore, it avoids the propagation of incorrect inputs. Simulations show an excellent performance of TL in the presence of large random noise at the inputs with a practical full tolerance to input with a signal to noise ratio of 5dB. Turtle Logic in accordance to Kullback Leibler Distance noise immunity measurement for a NOT gate is approximately 3.6X, 13.4X and 20.9X times better than MRF, DCVS and standard CMOS techniques, respectively, when the gates are operate, with a power supply of 0.15 volts, a temperature of 100 oC and noisy inputs with Additive White Gaussian Noise with zero mean and a standard deviation of 60mV.Peer ReviewedPostprint (published version