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The concept worked in this paper named Turtle Logic (TL) is a probabilistic logic method based on port redundancy and complementary data, oriented to emerging CMOS technologies and beyond, where the thermal noise could be predominant and the reliability of the future circuits will be limited. The TL is a technology independent method, which aims to improve tolerance to errors due to noise in single gates, logic and functional units. The TL operation is based on the consistency relation of redundant inputs. In case of discrepancy, the output of the system keeps the previous value. Therefore, it avoids the propagation of incorrect inputs. Simulations show an excellent performance of TL in the presence of large random noise at the inputs with a practical full tolerance to input with a signal to noise ratio of 5dB. Turtle Logic in accordance to Kullback Leibler Distance noise immunity measurement for a NOT gate is approximately 3.6X, 13.4X and 20.9X times better than MRF, DCVS and standard CMOS techniques, respectively, when the gates are operate, with a power supply of 0.15 volts, a temperature of 100 oC and noisy inputs with Additive White Gaussian Noise with zero mean and a standard deviation of 60mV.Peer ReviewedPostprint (published version

Abstract-As devices and operating voltages are scaled down, future circuits will be plagued by higher soft error rates, reduced noise margins and defective devices. A key challenge for the future technologies is to retain circuit reliability in the presence of faults and noise. The Turtle Logic (TL) is a new probabilistic logic method based on port redundancy and complementary data, oriented to emerging and beyond CMOS technologies. The TL is a technology independent method, which aims to improve tolerance to errors due to noise in single gates, logic blocks or functional units. The TL operation is based on the consistency relation of redundant inputs. In case of discrepancy, the output of the system keeps the previous value, therefore avoiding the propagation of incorrect inputs. Simulations show an excellent performance of TL in the presence of large random noise at the inputs, as well as intrinsic noise (thermal noise and flicker noise) and shot noise in the power source.

Abstract. All electronic processing components in future deep nanotechnologies will exhibit high noise level and/or low S/N ratios because of the extreme voltage reduction and the nearly erratic nature of such devices. Systems implemented with these devices would exhibit a high probability to fail, causing an unacceptably reduced reliability. In this paper we introduce an innovative input and output data redundancy principle for sequential block circuits, the responsible to keep the state of the system, showing its efficiency in front of other robust technique approaches. The methodology is totally different from the Von Neumann approaches, because element are not replicated N times, but instead, they check the coherence of redundant input data no allowing data propagation in case of discrepancy. This mechanism does not require voting devices. IntroductionFault-tolerance on semiconductor devices has been a key issue since upsets were first experienced in space applications several years ago. Since then, the interest in studying fault-tolerance techniques in order to keep the data integrity of integrated circuits operating in hostile environment has increased, driven by all possible applications of radiation tolerant circuits and the requirement of high reliability behaviour [1].In addition, because of the continuous shrinking evolution of the technology of semiconductor components as well as the reduction of voltage levels for energy saving purposes, the increase of speed and logic density [2], the need of fault-tolerant mechanisms is becoming a key remerging topic. As stated in [3], drastic device shrinking, power supply reduction and increasing operating speeds significantly reduce the noise margins and thus the reliability that very deep submicron (VDSM) ICs face from the various internal and external sources of noise. The basis of the robust design methodology presented in this paper is based on the use of redundant data expression L, over the whole set of logic elements in the system. This redundant input/output data mechanism is called port redundancy and in [4] it was demonstrated that an acceptable ratio between reliability improvement and hardware overhead can be accomplished just by duplicating the input and output data ports L=2.The design principle lies on the coherence enforcement of each pair of redundant inputs. All variables of input ports are expressed through their true and complement values (L=2), as well as their output variables, with a clear similarity with differential logic, but with behaviour of the processing blocks significantly different. In case any input port presents a discrepancy of logic values, the sequential elements holds the previous output values, hence refraining the propagation of incorrect inputs. Consequently in case of aggressions the memory elements present a shielding effect of the logic, and because of this behaviour we call the logic implemented with this principle turtle logic (TL). Sequential Logic ElementsThe principles of design of D-type flip-flops based on our...