Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits

Garcia-Leyva, Lancelot; Calomarde, Antonio; Moll, Francesc; Rubio, Antonio

doi:10.1109/mwscas.2010.5548845

Cited by 4 publications

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Section: Introductionmentioning

confidence: 99%

“…The basis of the robust design methodology presented in this paper is based on the use of redundant data expression L, over the whole set of logic elements in the system. This redundant input/output data mechanism is called port redundancy and in [4] it was demonstrated that an acceptable ratio between reliability improvement and hardware overhead can be accomplished just by duplicating the input and output data ports L=2.The design principle lies on the coherence enforcement of each pair of redundant inputs. All variables of input ports are expressed through their true and complement values (L=2), as well as their output variables, with a clear similarity with differential logic, but with behaviour of the processing blocks significantly different.…”

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confidence: 99%

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Robust Sequential Circuits Design Technique for Low Voltage and High Noise Scenarios

Garcia-Leyva

Rivera–Dueñas

Calomarde

et al. 2016

MATEC Web of Conferences

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Abstract. All electronic processing components in future deep nanotechnologies will exhibit high noise level and/or low S/N ratios because of the extreme voltage reduction and the nearly erratic nature of such devices. Systems implemented with these devices would exhibit a high probability to fail, causing an unacceptably reduced reliability. In this paper we introduce an innovative input and output data redundancy principle for sequential block circuits, the responsible to keep the state of the system, showing its efficiency in front of other robust technique approaches. The methodology is totally different from the Von Neumann approaches, because element are not replicated N times, but instead, they check the coherence of redundant input data no allowing data propagation in case of discrepancy. This mechanism does not require voting devices. IntroductionFault-tolerance on semiconductor devices has been a key issue since upsets were first experienced in space applications several years ago. Since then, the interest in studying fault-tolerance techniques in order to keep the data integrity of integrated circuits operating in hostile environment has increased, driven by all possible applications of radiation tolerant circuits and the requirement of high reliability behaviour [1].In addition, because of the continuous shrinking evolution of the technology of semiconductor components as well as the reduction of voltage levels for energy saving purposes, the increase of speed and logic density [2], the need of fault-tolerant mechanisms is becoming a key remerging topic. As stated in [3], drastic device shrinking, power supply reduction and increasing operating speeds significantly reduce the noise margins and thus the reliability that very deep submicron (VDSM) ICs face from the various internal and external sources of noise. The basis of the robust design methodology presented in this paper is based on the use of redundant data expression L, over the whole set of logic elements in the system. This redundant input/output data mechanism is called port redundancy and in [4] it was demonstrated that an acceptable ratio between reliability improvement and hardware overhead can be accomplished just by duplicating the input and output data ports L=2.The design principle lies on the coherence enforcement of each pair of redundant inputs. All variables of input ports are expressed through their true and complement values (L=2), as well as their output variables, with a clear similarity with differential logic, but with behaviour of the processing blocks significantly different. In case any input port presents a discrepancy of logic values, the sequential elements holds the previous output values, hence refraining the propagation of incorrect inputs. Consequently in case of aggressions the memory elements present a shielding effect of the logic, and because of this behaviour we call the logic implemented with this principle turtle logic (TL). Sequential Logic ElementsThe principles of design of D-type flip-flops based on our...

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Section: Introductionmentioning

confidence: 99%

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confidence: 99%

Robust Sequential Circuits Design Technique for Low Voltage and High Noise Scenarios

Garcia-Leyva

Rivera–Dueñas

Calomarde

et al. 2016

MATEC Web of Conferences

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“…Con el fin de comprobar el mejoramiento de la fiabilidad de un circuito por medio de la Lógica Tortuga (TL) se implementa una puerta lógica NOT con tres metodologías diferentes: estándar CMOS , MRF [63] y TL [64] usando puerta lógicas CMOS convencionales para implementar las tres técnicas. La Figura 5.5 muestra los resultados para una simulación transitoria SPICE usando los modelos de los dispositivos de una tecnología AMS de 90nm, un voltaje de polarización V DD de 0.5V y una temperatura de 100 o C. El ruido interno se genera mediante la opción de ruido transitorio, opción interna del simulador, la cual genera ruido intrínseco en cada transistor y en cada fuente de alimentación.…”

Section: Resultados De Simulación Para Una Implementación Basada En P...unclassified

Metodología de diseño lógico redundante para escenarios con ruido extremadamente alto y bajo voltaje de alimentación

García Leyva

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In future scenarios of low power and low voltage the electronic systems will present a high error ratio or voltage fluctuations due to dramatically signal to noise ratio. These transient errors can affect the logical results in a permanent way. In this thesis it has shown a new logic based on multiple redundant lines for each logical node as an alternative to strategies based on triple redundancy (TMR) within a fault-tolerant stage. The probability distribution of voltages in a noisy digital node can be described, as the union of two Gaussian distributions centred on the 0-and 1-logical, in terms of voltage are 0 and VDD, respectively. A digital circuit has an error when a logical value is misinterpreted, that is, when a 1-logic is interpreted as a 0-logical and viceversa, this is defined by the error probability Pe. One possible way to reduce the error probability for a noisy digital node is by increasing the number of ports n times that in this thesis is called as port redundancy PR-N). In a scenario with a very high noise level, for example for an SNR of -3 dB, conventional logic has a reliability loss of approximately 50%. Based on the reliability analysis in this work thesis, a new design paradigm named Turtle Logic, which is based on the complementary redundancy lines for each logical node, is presented. In this thesis it was demonstrated that an appropriate relationship between redundancy, complexity and hardware penalty is that all ports of the circuits make use of a redundant one in their ports (PR-1). Based on PR-1 the design methodology used in this thesis is the analysis of the logical coherence between the signals replicated by their true and complementary logical ports, either a logic gate, combinational circuit, circuit sequential or processor. Logical coherence or consistency is the logical values of each input and output always have complementary logical values, otherwise means has at least one error occurred. This logical concept is called Turtle logic because it's mimics the behaviour of the turtles in the wild life. This is when the turtles are in a dangerous situation; they remain in a state of self-protection. When the threat has disappeared turtles continue their normal life. Following this analogy when there is noise that causes incoherence values on complementary redundant signals, then the device (gate, combinational circuit, sequential element or processor) maintains its correct previous output logic values, and when the noise has a magnitude that does not cause an inconsistency in some of the complementary inputs, then the devices turtle continue their normal logic operation for which they were designed. Any logic function can be implemented following the methodology of Turtle logic design (PR1 and logical coherence). In order to build the basic logic elements by Turtle logic principles were built NOT, NAND2, NOR2 and XOR2 gates. According to the works of reliability based on the Turtle logic proposal and worked in this thesis, you have all the elements that integrate logic design any logic gate, combinational circuit, sequential circuit and processor, which exhibit high reliability in high noise scenarios and low supply voltage regarding versus Markov random fields, Triple redundancy, C-element and a standard logic methodologies. El multiplicador Baugh-Wooley es implementado por medio de cuatro estados pipeline. Cada estado pipeline procesa 4 bits de la operación de multiplicación. Dos metodologías son probadas mediante el multiplicador Baugh-Wooley, la convencional y Lógica Tortuga. Los multiplicadores bajo prueba se implementan en las mismas condiciones ya que permite una comparación directa en términos de fiabilidad: * Dos procesadores de ayuda, el primero suministra los datos de entrada al multiplicador bajo prueba, y el segundo es el que recibe los datos procesados por el mismo multiplicador. * Un protocolo de comunicación Handshake, basado en dos señales de control, Req y Ack. * Cuatro estados pipeline, en donde cada estado procesa 4 bits de la operación de multiplicación. * Tecnología CMOS de 90nm. * En el primer experimento se inyectan espurios a las líneas primarias de entrada de los dos multiplicadores. * En el segundo experimento se inyecta ruido aleatorio en los nodos internos de la segunda etapa pipeline de ambos multiplicadores. Se inyectan espurios en las líneas del bit menos y más significativo del primer y segundo nivel pipeline de ambos multiplicadores. * Cada experimento implica 1,000 muestras discrepantes simples para ambos multiplicadores y sólo para el multiplicador Tortuga, 1000 muestras discrepantes dobles. El tiempo inicial de cada discrepancia simple y doble, esta localizado de forma aleatoria dentro del periodo T. Las discrepancias inyectadas en el bit menos significativo (LSB) y en el bit más significativo (MSB) son independientes y en instantes de tiempo distintos. Para el caso del multiplicador Tortuga son considerados dos diferentes casos; en el primer caso la discrepancia es inyectada en sólo una de las líneas (línea verdadera del dato) y en el segundo caso la discrepancia es inyectada en ambas líneas del dato. Cada discrepancia es generada con el mismo principio de aleatoriedad y con independencia probabilística, por lo tanto, las señales discrepantes dobles son no correladas. Un severo modelo de ruido ha sido usado en los experimentos aplicado a una implementación de un multiplicador 8x8-bits pipelined Baugh-Wooley complemento a dos. Los experimentos revelan una tolerancia perfecta para el caso de discrepancias en líneas sencillas (sin errores a la salida de todos los casos) para ambos nodos primarios e internos con un costo de perdida de relojes, entre un 6% y un 25% para el ruido inyectado en los experimentos. Esto significa que las prestaciones del sistema disminuyen sin embargo mantiene un alto nivel de fiabilidad. Para el mismo experimento, un multiplicador convencional exhibe una alta relación de error entre un 6% y un 48%. La relación de error para la implementación lógica Tortuga propuesta con doble discrepancia en ambas líneas verdadera y complementaria, es menor que el 0.1% cuando el ruido afecta nodos de entrada primarios y es menor al 0.9% cuando el ruido afecta a nodos internos. Sólo discrepancias simultaneas para ambas líneas pueden generar un error. De acuerdo a los trabajos de fiabilidad con base a la lógica Tortuga , se obtuvieron todos los elementos de diseño lógico que permiten integrar cualquier puerta lógica, circuito combinacional, circuito secuencial y procesador.

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New redundant logic design concept for high noise and low voltage scenarios

Garcia-Leyva

Andrade

Fernandez

et al. 2011

Microelectronics Journal

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Turtle Logic: A new probabilistic design methodology of nanoscale digital circuits

Cited by 4 publications

References 5 publications

Robust Sequential Circuits Design Technique for Low Voltage and High Noise Scenarios

Robust Sequential Circuits Design Technique for Low Voltage and High Noise Scenarios

Metodología de diseño lógico redundante para escenarios con ruido extremadamente alto y bajo voltaje de alimentación

New redundant logic design concept for high noise and low voltage scenarios

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