Feasibility of Embedded DRAM Cells on FinFET Technology

Amat, E.; Calomarde, Antonio; Moll, Francesc; Canal, Ramón; Rubio, Antonio

doi:10.1109/tc.2014.2375204

Cited by 14 publications

(22 citation statements)

References 25 publications

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“…Intel Atom [6] Intel Nehalem [7] AMD Llano [8] Intel Broadwell [18] IBM Power [19] [20]). A mixed cell is defined as a cell where T1 is pMOS and the rest are nMOS.…”

Section: B Retention Time (Rt)mentioning

confidence: 99%

Modem Gain-Cell Memories in Advanced Technologies

Amat

Canal

Rubio

2018

2018 IEEE 24th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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With the advent of the slowdown in DRAM capacitor scaling [1] and the increased reliability problems of traditional 6T SRAM memories [2], industry and academia have looked for alternative memory cells. Among those, gaincells have attracted significant attention due to their smaller size (compared to SRAM) and non-destructive read operation (compared to DRAM) as well as considerable low power and reasonable robustness. This paper first summarizes the available evidences of SRAM and eDRAM in commercial and test chips. Then, it analyzes the performance, reliability and scaling of eDRAM gain-cells in 10 and 7 nm FinFET technology; as well as above and below VT (i.e. sub-threshold).

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“…Intel Atom [6] Intel Nehalem [7] AMD Llano [8] Intel Broadwell [18] IBM Power [19] [20]). A mixed cell is defined as a cell where T1 is pMOS and the rest are nMOS.…”

Section: B Retention Time (Rt)mentioning

confidence: 99%

Modem Gain-Cell Memories in Advanced Technologies

Amat

Canal

Rubio

2018

2018 IEEE 24th International Symposium on on-Line Testing and Robust System Design (IOLTS)

Self Cite

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“…Since the leakage current of the nMOS transistor is significantly higher than that of the pMOS transistor, alternate cell configurations that mix the transistor types (pMOS write transistor and nMOS transistors for the read path) achieve better memory cell performance than the nMOS-only design [2], [3]. The storage node capacitor (SN), formed by T2's gate capacitance and Fig.…”

Section: A 2t and 3t1d Gain Cellsmentioning

confidence: 99%

“…The values of µ lognormal and D0.998Q are scaled to [1,2] before taking the product to make it independent of units. A design with lower mean MEP energy and smaller discrepancy from Normal distribution will also have smaller value of MxD.…”

Section: Shrinking the Right Tail Of Mep Energy Distributionmentioning

confidence: 99%

“…Further, Amat et.al. [2] observed that the 3T1D gaincells exhibits better reliability in front of device variability and single event upsets than the 2T gain cell.…”

Section: Introductionmentioning

confidence: 96%

“…Achieving a smaller form factor and higher energy-efficiency is of prime importance in a bio-medical wearable devices. Recently, embedded-DRAM (e-DRAM) caches have been advocated as the successors of SRAM [2]- [6] considering their higher densities (> 2X) [7] and smaller leakage, due to fewer number of transistor. 3T1D e-DRAM gain-cell is shown to be capable of achieving access speeds comparable to 6T SRAM [6] and with larger device density [3].…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Statistical Analysis and Comparison of 2T and 3T1D e-DRAM Minimum Energy Operation

Rana

Canal

Amat

et al. 2017

IEEE Trans. Device Mater. Relib.

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Abstract-Bio-medical wearable devices restricted to their smallcapacity embedded-battery require energy-efficiency of the highest order. However, minimum-energy point (MEP) at sub-threshold voltages is unattainable with SRAM memory, which fails to hold below 0.3V because of its vanishing noise margins. This paper examines minimum-energy operation of 2T and 3T1D e-DRAM gain cells as an alternative to SRAM at 32nm technology node with different design points: up-sizing transistors, using high-Vth transistors, read/write wordline assists and temperature. First, the e-DRAM cells are evaluated without considering any process variations. The design-space is explored by creating a kriging meta-model to reduce the number of simulations. A full-factorial statistical analysis of e-DRAM cells is performed in presence of threshold voltage variations and the effect of upsizing on mean MEP is reported. Finally, it is shown that the product of the read and write lengths provides a knob for trade-off between energy-efficiency and reliable MEP energy operation.

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A 1‐GHz GC‐eDRAM in 7‐nm FinFET with static retention time at 700 mV for ultra‐low power on‐chip memory applications

Sany

Ebrahimi

2021

Circuit Theory & Apps

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Conventional static random‐access memory (SRAM) suffers from high leakage power in advanced complementary metal‐oxide‐semiconductor nodes. Meanwhile, gain‐cell embedded dynamic random‐access memory (GC‐eDRAM) is an area‐efficient alternative to SRAM, although it requires periodic refresh cycles. In this regard, this study proposes a fin field‐effect transistor (FinFET)‐based 5T GC‐eDRAM bitcell that addresses the leakage power issue of SRAM while avoiding the bandwidth‐consuming refreshes of GC‐eDRAM. Furthermore, for the feasibility of scaling down transistors, the gain‐cell design is based on the FinFET, which overcomes short‐channel problems. The proposed 5T bitcell provides additional internal feedback relative to the 4T all‐nMOS fully depleted‐silicon on insulator (FD‐SOI) gain cell to ensure the static retention of both “1” and “0” data. The 2‐kB array was simulated by employing a 7‐nm FinFET predictive technology model (PTM) using HSPICE. The simulation results show that the proposed 5T bitcell (at 0.7 V) enables over 13× smaller data retention power and 10× area reduction compared to the 4T all‐nMOS GC‐eDRAM cell in a 28‐nm FD‐SOI technology.

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Feasibility of Embedded DRAM Cells on FinFET Technology

Cited by 14 publications

References 25 publications

Modem Gain-Cell Memories in Advanced Technologies

Modem Gain-Cell Memories in Advanced Technologies

Statistical Analysis and Comparison of 2T and 3T1D e-DRAM Minimum Energy Operation

A 1‐GHz GC‐eDRAM in 7‐nm FinFET with static retention time at 700 mV for ultra‐low power on‐chip memory applications

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