A Low-Power Ternary Adder Using Ferroelectric Tunnel Junctions

Abstract

Computing systems are becoming more and more power-constrained due to unconventional computing requirements like computing on the edge, in-sensor, or simply an insufficient battery. Emerging Non-Volatile Memories are explored to build low-power computing circuits, and adders are one among them. In this work, we propose a low-power adder using a Ferroelectric Tunnel Junction (FTJ). FTJs are two-terminal devices where the data is stored in the polarization state of the device. An FTJ-based majority gate is proposed, which uses a current-mode sensing technique to evaluate the majority of the inputs. By conditionally selecting between the majority and its complement, an XOR operation is implemented, thereby achieving full-adder functionality. Since FTJ-based majority operation is slow, a ternary adder architecture is used to compensate for the speed loss. The ternary adder proposed by us has two stages of full adder and requires O(1) time for n-bit addition. The proposed adder is verified using a simulation in CMOS 130 nm technology. A 32-bit addition can be achieved in 100 μs and consumes 0.78 pJ, which is very power efficient (7.8 nW). The proposed adder can be used in applications where power consumption is crucial, and speed is not a strict requirement.

A Reference-less Sense Amplifier to Sense pA Currents in Ferroelectric Tunnel Junction Memories

“…As stated, the SA was designed in 130 nm CMOS technology. A Verilog-A model based on Preisach equations was used to simulate the FTJ device characteristics and the reader is referred to [2] for more details of the modelling methodology. The FTJ-model used in simulation were fitted to NaMLab devices which have a Tunneling Electro Resistance (TER) of ≈ 4 (100 pA and 25 pA read-out currents for the two polarization states).…”

“…The sense amplifier proposed in this work was designed for the FTJ prototype device manufactured in NaMLab which have read-out currents in pA range. More specifically, the READ current for the two states are 25 pA and 100 pA, respectively when a READ voltage of 2V is applied across the junction [2]. The FTJ device is fabricated with an access transistor (T access ) in a 1T-1FTJ configuration (Fig.…”

“…Although FTJ is one of the most energyefficient device as a memory device, it requires a large READ time. The READ current for both the states is in pA [2] to nA [3] range and a reasonably large time ( ≈ 50 -100µs ) must be given for efficiently differentiating between the two states.…”