A Low Power Test Pattern Generator for Minimizing Switching Activities and Power Consumption

Bhandari, Jugal Kishore; Chaitanya, M Krishna; Rao, G

doi:10.1109/icirca.2018.8597212

Cited by 8 publications

(3 citation statements)

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“…Bhandari et al [58] presented another variant of the random toggle rejects circuit. The random reject circuit is added for each shift register stage of LFSR.…”

Section: Low-pass Filtermentioning

confidence: 99%

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Developments in scan shift power reduction: a survey

Sontakke,

Dickhoff

2023

Bulletin EEI

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While power reduction during testing is necessary for today's low-power devices, it also lowers test costs. Scan-based methods are the most widely used approach for testing integrated circuits (IC). Test vectors are shifted into and out of scan chains bit by bit during shift operation. The time required for shift operation dominates the test time. With the geometries shrinking (7 nm→5 nm→3 nm→1.8 nm), ICs are required to be tested for newer defects, increasing test time. The most effective way to reduce test time for scan operation is to increase the frequency of the shift operation. Reduction in shift power enables scan operation to be performed with increased frequency, reducing test time, and test cost. This paper presents a survey of techniques proposed recently for shift power reduction. Various techniques, including special flip-flop usage, segmentation, reordering, and low-pass filter, are being reviewed. The techniques are organized based on main attributes to underscore their similarities and differences. Pros and cons in terms of complexities involved in their implementation are discussed. We believe this paper will provide a point of reference for further studies in scan shift power reduction and will be helpful to both industry and academia.

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“…Bhandari et al [58] presented another variant of the random toggle rejects circuit. The random reject circuit is added for each shift register stage of LFSR.…”

Section: Low-pass Filtermentioning

confidence: 99%

“…Figure 8. Low-pass filters, (a) filter with mux select from scan chain[57] and (b) filter with mux select from LFSR stage[58] …”

mentioning

confidence: 99%

Developments in scan shift power reduction: a survey

Sontakke,

Dickhoff

2023

Bulletin EEI

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“…The report [5] examines all significant ATPG approaches to determine which, when combined with BIST, would be best for a particular bit size CUT. The LP-PCBTVG (low power-positioned complements bits test vector generation) method proposed in reference [9] declines switching activity and power utilization by rising association in test vectors. In [10], a novel weighted pseudo-random TPG and reseeding approach for low power (LP) scan-based BIST is introduced.…”

Section: Introductionmentioning

confidence: 99%

Designing and Implementing a power Efficient BIST in a BCD Multiplier

SAM¹

2022

Preprint

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<p> On any chip, the number of transistors doubles every eighteen months according to Moore's law. When there are more transistors in a circuit, there is a higher probability that one of those transistors will have a fault. To avoid and detect possible errors,testing is required. To test the required circuit, the BIST (Built-in-Self-Test) energy saving design emplos a modified MISR as the ORA (Output Response Analyzer) and a bit-swapping LFSR as the TPG (Test Pattern Generator). In this paper, we select two circuits - a combined circuit and an 8x8 BCD multiplier as CUT (circuit under test). TPG generates test patters that are fed into CUT, hile ORA evaluates the data generated by CUT and checks for errors in the circuit, and generates a pass/fail signal. This BIST structure detects one of the errors in the circuit.All results are matched to Xilinx ISE Design Suite 14.7 using Verilog and integrated into Vivado 2018.2.<br> </p>

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