A low-power VLSI architecture for full-search block-matching motion estimation

Do, V.L.; Yun, K.Y.

doi:10.1109/76.709406

Cited by 103 publications

(37 citation statements)

References 9 publications

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“…3)). This search region has (2p + 1) (Fig.3), e.g., [P 1,1 , P 2,1 , P 3,1 , ..., P 16,1 ] is one such 128-bit data, which belongs to the column 1 of the search region. It is observed that the one of the columns from column number 17 to 32 are accessed concurrently with another column from rest of the columns, i.e., 1 to 16 and 33 to 48, in the pre-defined search region.…”

Section: Memory Organizationmentioning

confidence: 99%

“…Customizable low-power FPGA cores were proposed by [10]. The aforementioned FSBM architectures can be divided into two categories, namely, FPGA [7,8,9,10,11,17] and ASIC [4,15,18,2,3,20,5,19,13,1,6]. This work uses FPGA technology to implement a high-performance ME hardware with due consideration to (a) processing speed and (b) silicon area.…”

Section: Introuctionmentioning

confidence: 99%

“…A low-latency high-throughput tree architecture for FSBM was proposed in [3]. Both [13] and [1] proposed low-power architectures based on removal of unnecessary computations. Finally, a novel low-power parallel tree FSBM architecture was proposed in [6], which exploited the spatial data correlations within parallel candidate block searches for data sharing and thus effectively reduces data access bandwidth and power consumption.…”

Section: Introuctionmentioning

confidence: 99%

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Speed-area optimized FPGA implementation for Full Search Block Matching

Ghosh

Saha

2007

2007 25th International Conference on Computer Design

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IntrouctionRapid growth in High-Definition (HD) digital video applications has lead to an increased interest in portable HDquality encoder design. HD-compatible MPEG2 MP@HL encoder uses Full Search Block Matching Algorithm (FS-BMA) based Motion Estimation (ME). The ME module accounts for more than 80% of the computational complexity of a typical video encoder. Moreover, the power consumption of an FSBM-based encoder is prohibitively high, particularly for portable implementations. Hence, efficient ME processor cores need to be designed to realize portable HDTV video encoders.Parameterizable FSBM ASIC design to solve the input bandwidth problem by using on-chip line buffers was proposed in [15]. [18] proposed a family of modular VLSI architectures which allow sequential inputs but perform parallel processing with 100 percent efficiency. A systolic mapping procedure to derive FSBM architectures was proposed in [4]. The designs of ([2], [20]) and [5] focused on the reduction of pin counts by sharing memory units and 2-dimensional data reuse, respectively. [19] improved the memory bandwidth by using an overlapped data flow of search area which increased the processing element (PE) utilization. A low-latency high-throughput tree architecture for FSBM was proposed in [3]. Both [13] and [1] proposed low-power architectures based on removal of unnecessary computations. Finally, a novel low-power parallel tree FSBM architecture was proposed in [6], which exploited the spatial data correlations within parallel candidate block searches for data sharing and thus effectively reduces data access bandwidth and power consumption. [7] proposed an FPGA architecture to implement parallel computation of FSBM. Systolic array and novel OnLine Arithmetic (OLA) based designs for FSBM were proposed in [8] and [9], respectively. Customizable low-power FPGA cores were proposed by [10]. The aforementioned FSBM architectures can be divided into two categories, namely, FPGA [7,8,9,10,11,17] and ASIC [4,15,18,2,3,20,5,19,13,1,6]. This work uses FPGA technology to implement a high-performance ME hardware with due consideration to (a) processing speed and (b) silicon area. Almost all aforementioned VLSI architectures optimize any one of these parameters. The novelty of the proposed architecture lies in its combined optimization of the aforementioned conflicting design requirements. The proposed hardware uses an initially-split pipeline to reduce processing cycles for each MB and thus increases the throughput. In addition, this design requires less number of adders and only one Absolute Difference (AD) PE, which drastically reduces the silicon area when compared to other existing designs. The pixels of the search regions have been organized in memory banks such that two sets of 128-bit (16 8-bit pixels) data can be accessed in each clock cycle.Section 2 gives an overview of FSBM-based motion estimation. Section 3 presents a brief discussion on SAD modifications and describes the proposed FSBM hardware. The implementation and comparative...

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Section: Memory Organizationmentioning

confidence: 99%

Section: Introuctionmentioning

confidence: 99%

Section: Introuctionmentioning

confidence: 99%

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Speed-area optimized FPGA implementation for Full Search Block Matching

Ghosh

Saha

2007

2007 25th International Conference on Computer Design

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“…For example, reference [85] depicted a type D architecture and implemented the FSBMA with discrete TTL components. Reference [86] combined the architecture in [76] with the MSEA to avoid the unnecessary SAD computations for low power consumption. Reference [87] designed a powerful FSBMA chip with 1024 PEs to provide computational capability of 165 GOPS.…”

Section: Fsbma Architecturesmentioning

confidence: 99%

Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results

Huang

Chen

Tsai

et al. 2006

J VLSI Sign Process Syst Sign Image Video Technol

139

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Abstract. Block matching motion estimation is the heart of video coding systems. During the last two decades, hundreds of fast algorithms and VLSI architectures have been proposed. In this paper, we try to provide an extensive exploration of motion estimation with our new developments. The main concepts of fast algorithms can be classified into six categories: reduction in search positions, simplification of matching criterion, bitwidth reduction, predictive search, hierarchical search, and fast full search. Comparisons of various algorithms in terms of video quality and computational complexity are given as useful guidelines for software applications. As for hardware implementations, full search architectures derived from systolic mapping are first introduced. The systolic arrays can be divided into inter-type and intra-type with 1-D, 2-D, and tree structures. Hexagonal plots are presented for system designers to clearly evaluate the architectures in six aspects including gate count, required frequency, hardware utilization, memory bandwidth, memory bitwidth, and latency. Next, architectures supporting fast algorithms are also reviewed. Finally, we propose our algorithmic and architectural co-development. The main idea is quick checking of the entire search range with simplified matching criterion to globally eliminate impossible candidates, followed by finer selection among potential best matched candidates. The operations of the two stages are mapped to the same hardware for resource sharing. Simulation results show that our design is ten times more area-speed efficient than full search architectures while the video quality is competitively the same.

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“…For example, reference [11] is the extension of [5]. Reference [12] is proposed based on [9], and reference [13] combined [10] with multilevel successive elimination algorithm [14], [15]. Reference [16] is the extension of [6].…”

Section: Impact Of Supporting Vbsme In Different Hardware Architementioning

confidence: 99%

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Chen

Chien

Huang

et al. 2006

IEEE Trans. Circuits Syst. I

211

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Abstract-Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intralevel classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.Index Terms-Block matching, H.264/AVC, motion estimation (ME), variable block size, very large scale integration (VLSI) architecture.

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A low-power VLSI architecture for full-search block-matching motion estimation

Cited by 103 publications

References 9 publications

Speed-area optimized FPGA implementation for Full Search Block Matching

Speed-area optimized FPGA implementation for Full Search Block Matching

Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

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