Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Abstract

Abstract-Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intralevel classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.Index Terms-Block matching, H.264/AVC, motion estimation (ME), variable block size, very large scale integration (VLSI) architecture.

High-Performance Motion Estimation for Image Sensors with Video Compression

“…Different pixels can be computed in parallel to get SAD between two MBs. A typical implementation of Level A is an N × N PEA with an adder tree [25]. Level B is the parallelism among reference blocks.…”

“…Level C cannot be directly applied to VC-ME because of data dependency between adjacent CBs. After modifying the method of computing the MV predictor [25], data dependency is eliminated and Level C can be applied to VC-ME. Level D is the parallelism among frames.…”

“…Previous work mainly focused on intra-frame data reuse within a reference frame but inter-frame data reuse was neglected. For VC-ME, the reconstructed frame was usually stored to off-chip memory and then loaded to on-chip memory when needed [23,25,26,27,28]. If the reconstructed frame is reused on chip without being stored to off-chip memory for VC-ME, the off-chip memory traffic will be greatly reduced.…”

Low complexity video coding on Block based Singular Value Decomposition (SVD) Algorithm

“…Current work includes optimizing the bit usage and modifying the motion vector sort algorithm to support random errors [4]. Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design [5]. ].…”

Prototyping design of a flexible DSP block with pipeline structure for FPGA

“…Multi-Operand addition occurs in a variety of signal processing applications, such as FIR filters [4]; Arithmetic transformations [5]; motion estimation [6] and correlators used in wireless communication [7]; In commercial FPGA device, multi-operand addition is realized on general logic resource, which is comprised of LUTs and carry chains [8,9,10], so the performance is limited.…”