A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA

Parsakordasiabi, Mojtaba; Vornicu, Ion; Rodríguez-Vázquez, Á.; Carmona-Galán, Ricardo

doi:10.3390/s21010308

Cited by 29 publications

(14 citation statements)

References 38 publications

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“…In terms of the dead time, there are a minimum of two clock cycles in other schemes, except for one cycle in this work and the literature [29]. As for the resolution and accuracy, this study is slightly inferior to the literature [37,40], but the resource overhead of a single chain is lower than the literature [40]. Regarding the nonlinearity and resource cost of switching to a uniform scale, the results in this work are more ideal than that of most schemes.…”

Section: Experimental Comparison Of Tdc In Recent Yearsmentioning

confidence: 71%

Design of a high-accuracy time-to-digital converter based on dual-edge signals

et al. 2023

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Among numerous time-to-digital converters (TDC), tapped delay line (TDL) is the most commonly used architecture. However, its dead time of more than two cycles is inefficient for applications with high measurement rates. Limited by the device process, the delay of each cell in the TDL exhibits a random and uneven distribution, degrading the linearity of the TDC. In this study, a dual-edge TDL structure is proposed. By improving original pulse-holding circuit, the propagated signal injected into the fine measurement chain is alternately switched between rising and falling edge signals to decrease the dead time to one cycle. The nonlinearity problem is alleviated by an enhanced tapped sampling sequence circuit. A dual-edge “1” count encoder is introduced to effectively simplify the difficulty of addressing the bubble problem. Bit-by-bit calibration and a moving average filter are adopted to improve accuracy. The proposed scheme has been verified on a Xilinx Kintex-7 FPGA platform. The resolution (least significant bit, LSB1) is 12.07 ps when the propagated signal in the TDL is the rising edge. The differential nonlinearity (DNL) is [-0.81,0.93] LSB1, and the integral nonlinearity (INL) is between [-2.33,2.19] LSB1. At the falling edge, the resolution (LSB0) is 11.90 ps, between [-0.73,0.98] LSB0 and [-2.46,1.83] LSB0 for DNL and INL, respectively. In addition, the accuracy reaches 15.25 ps after multiple measurements for different time intervals separately.

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Section: Experimental Comparison Of Tdc In Recent Yearsmentioning

confidence: 71%

Design of a high-accuracy time-to-digital converter based on dual-edge signals

et al. 2023

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“…The measurement distribution of the TDC bin in terms of DNL and INL are visualized in Figure 12 . The DNL and INL values are calculated by Equations (9) and (10) as follows [ 1 , 37 , 42 ]:

…”

Section: Resultsmentioning

confidence: 99%

“…The INL in the range of [−25.44, +26.24] LSB, and the INL peak-to-peak of our TDC is in range of 51.68 LSB. A calibration table based on the measured INL is created to remove measurement errors [ 42 ].…”

Section: Resultsmentioning

confidence: 99%

A Size, Weight, Power, and Cost-Efficient 32-Channel Time to Digital Converter Using a Novel Wave Union Method

Alshahry,

Alshehry,

Alhazmi

et al. 2023

Sensors

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We present a Tapped Delay Line (TDL)-based Time to Digital Converter (TDC) using Wave Union type A (WU-A) architecture for applications that require high-precision time interval measurements with low size, weight, power, and cost (SWaP-C) requirements. The proposed TDC is implemented on a low-cost Field-Programmable Gate Array (FPGA), Artix-7, from Xilinx. Compared to prior works, our high-precision multi-channel TDC has the lowest SWaP-C requirements. We demonstrate an average time precision of less than 3 ps and a Root Mean Square resolution of about 1.81 ps. We propose a novel Wave Union type A architecture where only the first multiplexer is used to generate the wave union pulse train at the arrival of the start signal to minimize the required computational processing. In addition, an auto-calibration algorithm is proposed to help improve the TDC performance by improving the TDC Differential Non-Linearity and Integral Non-Linearity.

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“…Table I concludes the performance of the implemented FPGA TDC along with its prior arts for easy comparison. Even though realized with less advanced process nodes, the [13] '21 [14] '20 [16] '20 [19] '19 [20] '20 [21] '19 [24] '21 [25] '18 [28] '17 [37] '17 [38] '18 [39]…”

Section: Measurement Resultsmentioning

confidence: 99%

A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection

et al. 2022

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A field-programmable gate array (FPGA) high-resolution time-to-digital converter (TDC) based on phase-wrapping, sorting, and selection to achieve an extremely fine bin size of 1 ps is proposed in this paper. Based on Nutt interpolation method, a wide measurement range with a high resolution can be realized at the same time. The input signal is fed into tapped delay lines (TDL) with regularized and automated cell placements to generate a multitude of delayed signals with plenty of regularized phase shifts. Due to periodicity, those phase shifts will be equivalently wrapped within a reference clock period and then phase sorting, ROM-based selection are applied to construct a merged TDL with uniform phase division across the reference clock period. The FPGA TDC was implemented successfully on both Altera Stratix IV to achieve a resolution as fine as 1ps with a measurement range of 1s. The short-range integral non-linearity errors (INL) are measured as -1.470 -1.676 LSB for Stratix IV to demonstrate its excellent linearity.INDEX TERMS Field programmable gate array (FPGA), merged TDL, phase selection, phase sorting, phase wrapping, time-to-digital converter.

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A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA

Cited by 29 publications

References 38 publications

Design of a high-accuracy time-to-digital converter based on dual-edge signals

Design of a high-accuracy time-to-digital converter based on dual-edge signals

A Size, Weight, Power, and Cost-Efficient 32-Channel Time to Digital Converter Using a Novel Wave Union Method

A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection

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