A low settling time switching scheme for SAR ADCs with reset‐free regenerative comparator

Abstract

Summary This paper presents an energy‐efficient fully differential switching scheme for successive approximation register (SAR) analog‐to‐digital converters (ADCs). During the sampling phase, the top and bottom plates of all capacitors except most significant bit (MSB) capacitors are grounded in digital‐to‐analog converter (DAC) arrays. The input signals are bottom plate sampled on MSB capacitors. This technique can reduce the settling time by more than 87.5% in comparison with the conventional switching scheme. Furthermore, a novel reset‐free regenerative comparator is unveiled in this paper. The proposed comparator is armed to amplify its inputs both during the reset and evaluation phases. In comparison with a conventional single‐ended comparator, the proposed comparator can reduce power consumption above 90% for the almost same input‐referred offset voltage. The proposed scheme is designed with a resolution of 8‐bit and a sampling rate of 90 MS/s in a standard 65‐nm CMOS technology. The simulation results certify that the ADC dissipates 363‐μW power with a 1.2‐V supply voltage and achieves a 7.13 effective number of bits (ENOBs), yielding a 28.8 fJ/conversion step Nyquist rate Walden FOM.

High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

“…In applications like telecommunications, multimedia processing, sensor networks, and measurement systems where accurate and dependable conversion of analog signals is necessary, high-resolution ADCs are essential. These ADC's offer a way to precisely represent analog data in digital form, al-lowing for effective information processing, storage, and transfer [3,4]. The SAR ADC architecture is a preferred option for high-speed applications due to its widespread recognition of efficiency.…”

A 9-10-Bit Adjustable and Energy-Efficient Switching Scheme for Successive Approximation Register Analog-to-Digital Converter with One Least Significant Bit Common-Mode Voltage Variation

“…In the energy consumption analysis of the SAR ADC, it was learned that the capacitor array DAC consumed about 30% of the overall energy consumption [ 7 , 8 , 9 ], while the simulation energy analysis of the chip found that the DAC’s energy consumption was closer to 70% of the total energy consumption [ 10 , 11 , 12 ], coupled with the fact that it was relatively difficult to improve the structure of the analog module circuit.…”

A rail‐to‐rail regenerative comparator with inverse inverter pre‐amplifier for low supply voltage applications

“…Although this comparator has an easy-to-design structure, it consumes a considerable current at the evaluation phase, especially with low input common-mode voltages. Furthermore, it has a limited common-mode range which is important for many applications like successive approximation register analog to digital converters (SAR ADCs) [2]. A rail-to-rail operation is achieved by applying a bulk-driven technique at the expense of low energy efficiency [3].…”