A low spurious and small step frequency synthesizer based on PLL-DDS-PLL architecture

Abstract

This paper describes a low spurious and small step frequency synthesizer module based on PLL (Phase-Locked Loop)-DDS (Direct Digital Synthesis)-PLL structure, which is controlled by the parallel port of the computer. The module consists of four parts: the first PLL (PLL1), the DDS, the second PLL (PLL2) and the control part. The spurious of this module is ameliorated to some extent in comparison with traditional synthesizer technologies using single PLL. The experimental measurement of the actual module shows that the spurious is as low as 65dBc. In addition, its frequency range is 2060MHz-2160MHz, the frequency step size 10 kHz, the phase noise 90dBC/Hz@10kHz and the harmonics 40dBc.

A Wideband Frequency Synthesizer with High Frequency Resolution

“…In this article, a 1–2 GHz frequency synthesizer is designed and implemented, and DDS is used as a fractional divider in the PLL. Compared to the frequency synthesizers proposed in article , this L‐band frequency synthesizer has lower in‐band phase noise (assuming reduced 20 dB/decade), higher‐frequency resolution, lower spurious. Although the phase noise is worse than that in article , this structure is much simpler.…”

“…Over the past few years, many DDS+PLL techniques have been proposed, including using DDS as a reference for PLL , using DDS up‐converted by a mixer as PLL's reference , using DDS as a fractional divider in the PLL feedback path , and using DDS mixed in the PLL feedback path. In , the VCO output frequency is converted to a much lower frequency with an offset frequency source which minimizes the frequency division ratio to get low phase noise.…”