A low voltage 0.8V RF receiver in 28nm CMOS for 5GHz WLAN

Shirane, Atsushi; Kawai, S.; Aoyama, Hiromitsu; Ito, Ryoko; Mitomo, Toshiya; Kobayashi, Hiroyuki; Yoshida, Hiroshi; Majima, H.; Fujimoto, Ryuichi; Tsurumi, Hiroshi

doi:10.1109/esscirc.2017.8094592

Cited by 3 publications

(2 citation statements)

References 9 publications

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“…Supply voltage shrinkage is a prevalent approach in RF transceiver design for lowering the power consumption of portable wireless devices, in which a long charging cycle is a primary goal among all the performances [1~8]. Furthermore, a lower supply voltage is inevitable due to breakdown issues in modern deepsubmicron processes [9,10]. Unfortunately, the threshold voltage is not much reduced in consideration of current leakage.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 0.6V high-swing gate-switching charge pump for PLL with current self-matching technique in 28nm CMOS

Zhu

Chen

Zhao

et al. 2021

IEICE Electron. Express

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Section: Introductionmentioning

confidence: 99%

“…Unfortunately, the threshold voltage is not much reduced in consideration of current leakage. This brings great difficulties to assign adequate voltage headroom for conventional analog circuits [9].…”

Section: Introductionmentioning

confidence: 99%

A 0.6V high-swing gate-switching charge pump for PLL with current self-matching technique in 28nm CMOS

Zhu

Chen

Zhao

et al. 2021

IEICE Electron. Express

View full text Add to dashboard Cite

An 802.11ax 4 <inline-formula> <tex-math notation="LaTeX">$\times$ </tex-math> </inline-formula> 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer

Kawai

Ito

Nakata

et al. 2018

IEEE J. Solid-State Circuits

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A Parallel Sliding-IF Receiver Front-End With Sub-2-dB Noise Figure for 5–6-GHz WLAN Carrier Aggregation

Yang

Boon

et al. 2021

IEEE J. Solid-State Circuits

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This article presents a parallel sliding-IF 5-6-GHz wireless local area network (WLAN) receiver front-end supporting two-band carrier aggregation (CA), which alleviates potential local oscillator (LO) pulling and crosstalk problems. The supported frequency spacing between any two different carriers ranges from tens to hundreds of MHz. First, a complementary current-reused single-ended LNA with very low noise figure (NF) is developed to guarantee a low noise performance. Second, an active balun-splitter establishes a bridge between the LNA and the following parallel fully differential downconversion paths. Next, to optimize the performance of the passive double-conversion mixer, a detailed analysis has been conducted and shown that the time offset with specific values between the two LOs maximizes conversion gain and minimizes noise contribution, which enhances harmonic rejection simultaneously. Fabricated in 65-nm CMOS technology, this receiver front-end achieves an average 1.9-dB NF with a 39-dB gain at 5-6 GHz for single-carrier scenario, degraded by 0.4 dB with 35-dB gain for two-band CA scenario. It consumes 35 and 60 mA with 1.2-V supply for single carrier and two-band CA scenario, respectively. The total area is 0.56 mm 2 .

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A low voltage 0.8V RF receiver in 28nm CMOS for 5GHz WLAN

Cited by 3 publications

References 9 publications

A 0.6V high-swing gate-switching charge pump for PLL with current self-matching technique in 28nm CMOS

A 0.6V high-swing gate-switching charge pump for PLL with current self-matching technique in 28nm CMOS

An 802.11ax 4 <inline-formula> <tex-math notation="LaTeX">$\times$ </tex-math> </inline-formula> 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer

A Parallel Sliding-IF Receiver Front-End With Sub-2-dB Noise Figure for 5–6-GHz WLAN Carrier Aggregation

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