A Low-Voltage PLL Design Using a New Calibration Technique for Low-Power Implantable Biomedical Systems

This paper presents a novel jitter reduction technique for a voltage-controlled ring oscillator (VCRO). This technique is helpful in employing VCRO-based circuits like Analog to Digital Converter (ADC), Phase Locked Loop (PLL) and time-based circuits whose performance is severely degraded by high jitter. In the proposed technique, the jitter is extracted using Excess Phase Discrimination (EPD) block and is transformed into Pulse Width Modulated (PWM) signal, which is then fed into the Phase Compensator (PC) block. This block reduces the jitter by about half its value after enabling the Single Ended Injection Locking (SEIL). The proposed work is designed in SCL 180[Formula: see text]nm CMOS technology at 1.8 V supply. On enabling the proposed circuit, the Root Mean Square (RMS) jitter reduces from 5.94 to 2.58 ps (about 56%) for VCRO running at 58 MHz and consumes a total power of 375.84 [Formula: see text]W. The overall performance of the proposed circuit does not vary much in the post-layout simulations, hence demonstrating the effectiveness of the proposed technique.

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A Low-Voltage PLL Design Using a New Calibration Technique for Low-Power Implantable Biomedical Systems

Cited by 5 publications

References 21 publications

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