A <inline-formula> <tex-math notation="LaTeX">$3\times 60\;\text{Gb/s}$</tex-math> </inline-formula> Transmitter/Repeater Front-End With <inline-formula> <tex-math notation="LaTeX">$4.3\;{\rm V}_{\rm PP}$</tex-math> </inline-formula> Single-Ended Output Swing in a 28nm UTBB FD-SOI Technology

Abstract

A versatile three-lane transmitter/repeater array was designed and manufactured in a production 28nm ultra-thin body and BOX (UTBB) FD-SOI CMOS technology. Each lane in the array can operate at 60 Gb/s with adjustable output swing between 2.6 and 4.3 VPP with a measured input sensitivity of 10 mVPP at 40 Gb/s, and requires at least 40mVPP input signal level to fully saturate the output driver for maximum swing operation at 60 Gb/s. Scaled, cascaded single-ended CMOS inverter transimpedance amplifiers with resistive and inductive feedback and interstage series inductive peaking were used to form the preamplifiers of each lane. These were optimized for maximum bandwidth and large gain, and drive the >4V PP swing seriesstacked cascoded CMOS inverter output stage. The single-ended CMOS-inverter topologies ensure that the total power consumption scales with the data rate and reduce the lane footprint to that of a ground-signal pad I/O. The measured lane-to-lane isolation is better than 40 dB up to 55 GHz, while the measured Tx-toRx dynamic range, defined as the ratio of the maximum output swing and corresponding minimum input voltage and sensitivity, is larger than 54 dB up to 40 Gb/s.

CMOS Inverter as Analog Circuit: An Overview

“…Then, the input-referred noise is obtained by dividing (1) with the trans-impedance gain R as: Nowadays, in order to take advantage of the CMOS inverter in modern process technology, there has been a lot of approaches to adopt CMOS inverter into analog circuits. This paper focuses on the applications of high-speed analog circuits, and introduces three examples of that, amplifier in optical communication receivers [6,[14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30], high-speed clock and data buffer [13,[31][32][33][34][35][36][37][38][39][40][41], and output driver for high-speed I/O transmitter [13,40,[42][43][44][45][46][47][48][49][50].…”

“…As a result, such inductive feedback leads to a high-frequency peaking, which can be used to compensate the dominant pole by the C PD . Recent state-of-the-arts works in [15,24,29] have combined the series peaking and the inductive feedback, and therefore considerable high-bandwidth at a quite impressive energy efficiency is achieved. Moreover, the authors in [29] saved inductor area by incorporating T-coil inductive peaking.…”

A DC-coupled 50 Gb/s 0.064 pJ/bit thin-oxide level shifter in 28 nm FDSOI CMOS

“…Together with the increasing data rates, comes the challenge to increase the power efficiency and the integration density. Recently CMOS-based transceivers have shown bit rates exceeding 40 Gb/s at 2 pJ/bit or less [1,2,3]. To realize this low power consumption, high speed CMOS transceivers rely on multi-stage inverter based topologies.…”

“…To generate a driving voltage that is larger than 1 V with inverter based driver circuits, a cascoded inverter driver (Fig. 1) [2,6,7] or a pseudo differential output driver [8,9] can be used.…”

“…Generating this level shifted signal proves to be difficult for high speed applications. To obtain the required bandwidth an AC coupled level shifter [2,6,10] is frequently implemented, but can introduce bit errors when sending bit streams with a long sequence section of consecutive identical bits if not sized properly or working at a lower rate than designed for. DC-coupled level shifters [7,11] do not have this problem and hence work for multi-rate applications, but are typically limited in maximum speed.…”