A MAC unit with double carry-save scheme suitable for 6-input LUT based reconfigurable systems

Cini, Ugur; Kurt, Olcay

doi:10.1109/icecs.2015.7440400

Cited by 2 publications

(12 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Hardware multiplier based MAC unit with pipeline is fast, however, the proposed scheme is 25 per cent faster if pipeline is employed in the multi-operand adders. Moreover, the proposed scheme is faster than redundant MAC unit in [13] also requires much less logic elements. The results reveal that, proposed double carry-save redundant representation provides good performance metrics among the carry-propagate multipliers and hardware multiplier based implementations.…”

Section: Resultsmentioning

confidence: 99%

“…Next, multiply and accumulate operations are unified under the (6, 3) counter tree arrays. The reason for the usage of (6, 3) counters for the operations is that, (6,3) counter synthesis is very effective in 6-input based LUT structures, which is most popular for high performance reconfigurable systems [12,13].…”

Section: Redundant Carry-save Mac Architecturementioning

confidence: 99%

“…If area requirement is not main concern, redundant reduction trees, such as (4, 2) compressors, binary-signed digit adder trees, counter trees can be used in FPGA multipliers. It is shown in [13] that (6,3) counters are very effective for the redundant addition operations and partial product reduction.…”

Section: Redundant Carry-save Mac Architecturementioning

confidence: 99%

“…Here, each line represents generated partial product. The Booth encoding scheme is also explained in detail in [13].…”

Section: Redundant Carry-save Mac Architecturementioning

confidence: 99%

See 3 more Smart Citations

MAC unit for reconfigurable systems using multi-operand adders with double carry-save encoding

Cini

Kurt

2016

2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

Self Cite

View full text Add to dashboard Cite

In this work, carry-free redundant arithmetic based fused multiply-accumulate (MAC) units are designed. In the first design, a regular redundant carry-save MAC unit is designed using well known carry-save techniques. In the second design, a hybrid design is proposed to exploit fast carry chains of the FPGA together with double carry-save output encoding. The proposed scheme exploits fast-carry chains of the FPGA structure, and, multi-operand adders are divided into smaller blocks to increase the performance. The outputs of the multi-operand adders are not merged and the results are kept in double carry-save format where extra redundancy reduces critical path delay. Designed MAC units have 16x16bit multiplier with 40-digit accumulate output for recursive multiply-add operations. The designs are synthesized on Altera TM Stratix III FPGAs and provide superior performance compared to conventional pipelined carry-propagate multiplyaccumulate units. The fusion in the arithmetic structure provides best performance compared to conventional pipelined multiplier based structures, hard multiplier based MAC units, and carry free redundant arithmetic based MAC structures as well.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Redundant Carry-save Mac Architecturementioning

confidence: 99%

Section: Redundant Carry-save Mac Architecturementioning

confidence: 99%

“…Here, each line represents generated partial product. The Booth encoding scheme is also explained in detail in [13].…”

Section: Redundant Carry-save Mac Architecturementioning

confidence: 99%

See 2 more Smart Citations

MAC unit for reconfigurable systems using multi-operand adders with double carry-save encoding

Cini

Kurt

2016

2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

Self Cite

View full text Add to dashboard Cite

show abstract

“…Although optimization over carry-save adder schemes are implemented, the area requirement is still higher than carry propagate scheme. In [8] and [9] it is reported that (6,3) counter arrays give best performance result for the reduction of partial products and multi-operand addition input operand reduction, whenever 6-input LUT structures are implemented. In [9], register-to-register delays for various reduction schemes are analysed, which gives (6, 3) reduction gives best performance result.…”

Section: Introductionmentioning

confidence: 99%

Limited Carry-Propagate Multiply-Accumulate Unit Design for Reconfigurable Systems

Cini¹,

Koçyiğit²

2017

ElAEE

Self Cite

View full text Add to dashboard Cite

Counter and compressor arrays are frequently employed in multiplier design to efficiently reduce partial products in VLSI design. On the other hand, in reconfigurable systems, fast carry chains boost the performance of carrypropagate adders. So that, in reconfigurable systems, to save logic element area, counter and compressor trees are not employed as much since they require more area than carrypropagate scheme. In this work, carry-propagate multioperand adders are employed in smaller blocks and the outputs are merged using double carry-save encoding to increase performance in reconfigurable systems. Hence, a more compact structure is achieved, compared to full redundant partial product reduction scheme providing comparable speed performance with counter array based carry-save structure. To show the effectiveness of the implementation, fused multiplyaccumulate (MAC) units are designed for various bit-widths. The structure is implemented on Altera TM Stratix III and Cyclone III FPGAs and the results show that, using least depth of pipeline, the throughput is better than regular carrypropagate and fully redundant carry-save reduction schemes.

show abstract

A MAC unit with double carry-save scheme suitable for 6-input LUT based reconfigurable systems

Cited by 2 publications

References 9 publications

MAC unit for reconfigurable systems using multi-operand adders with double carry-save encoding

MAC unit for reconfigurable systems using multi-operand adders with double carry-save encoding

Limited Carry-Propagate Multiply-Accumulate Unit Design for Reconfigurable Systems

Contact Info

Product

Resources

About