A Machine-Learning-Resistant 3D PUF with 8-layer Stacking Vertical RRAM and 0.014% Bit Error Rate Using In-Cell Stabilization Scheme for IoT Security Applications

Yang, Jianguo; Lei, Dengyun; Chen, Deyang; Li, Jing; Jiang, Haijun; Ding, Qingting; Luo, Qing; Xue, Xiaoyong; Lv, Hangbing; Zeng, Xiaoyang; Liu, Ming

doi:10.1109/iedm13553.2020.9372107

Cited by 11 publications

(15 citation statements)

References 7 publications

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“…The device switching power consumption was approximately 2.4 aJ for the set process and 7.9 aJ for the reset process. It is comparable to the best ultralow-power devices reported in this field (Table 1; see text S2 for calculation) (34)(35)(36)(37). Because the DC operation can provide a stable and large dynamic range, the devices are operated using DC I-V operation for further computing demonstration.…”

Section: Characteristics Of the Srm Arraysupporting

confidence: 79%

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Sparse matrix multiplication in a record-low power self-rectifying memristor array for scientific computing

Ren

et al. 2023

Sci. Adv.

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Memristor-enabled in-memory computing provides an unconventional computing paradigm to surpass the energy efficiency of von Neumann computers. Owing to the limitation of the computing mechanism, while the crossbar structure is desirable for dense computation, the system’s energy and area efficiency degrade substantially in performing sparse computation tasks, such as scientific computing. In this work, we report a high-efficiency in-memory sparse computing system based on a self-rectifying memristor array. This system originates from an analog computing mechanism that is motivated by the device’s self-rectifying nature, which can achieve an overall performance of ~97 to ~11 TOPS/W for 2- to 8-bit sparse computation when processing practical scientific computing tasks. Compared to previous in-memory computing system, this work provides over 85 times improvement in energy efficiency with an approximately 340 times reduction in hardware overhead. This work can pave the road toward a highly efficient in-memory computing platform for high-performance computing.

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Section: Characteristics Of the Srm Arraysupporting

confidence: 79%

“…2C. Commonly, the SRMs exhibit forming-free characteristics (27)(28)(29)(30)(31)(32)(33)(34)(35) similar to the proposed SRM cell, as shown in Fig. 2D.…”

Section: Characteristics Of the Srm Arraymentioning

confidence: 53%

Sparse matrix multiplication in a record-low power self-rectifying memristor array for scientific computing

Ren

et al. 2023

Sci. Adv.

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“…In addition, the computational parallelism is eventually restricted by the 2-D array structure. By leveraging the superior 3-D integration ability of the SRM devices [39][40][41][42] , we envisage a signi cant improvement in computational parallelism by mapping different rows of the compression matrix to different layers of a 3-D array. Furthermore, the computation can be completed in one step by simultaneously accessing different layers of the 3-D array.…”

Section: Solving Large-scale Sparse Matrix Equationmentioning

confidence: 99%

In-memory sparse matrix multiplication with a low-power self-rectifying memristor array

Ren

et al. 2022

Preprint

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Memristor-enabled in-memory computing provides an unconventional computing paradigm to surpass the energy efficiency of von Neumann computers. However, owing to the physical limitation of the crossbar structure, although the memristor array is desirable for dense computation, it suffers from significant performance degradation in both energy and area efficiency when processing sparse linear algebra operations. In this work, we report a highly efficient in-memory sparse computing system based on the self-rectifying memristor, which originates from the joint effort of devices and algorithms and is used to solve computational modelling problems. This system is expected to have 74.9 – 19.6 TOPS / W energy efficiency for 2-bit to 8-bit sparse computation in computational modelling tasks. Compared to the previous in-memory computing hardware, our system provides over one order of magnitude improvement in energy efficiency with more than two orders of magnitude reduction in hardware overhead. This work could pave the road towards a highly efficient, unconventional computing solution for high-performance computing.

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“…Nevertheless, because of their high intrinsic resistance, the current flowing through SRMs is typically low, which poses a considerable challenge to the peripheral sensing circuit. [65,101,105,132,[156][157] Additionally, as an undesirable issue for ideal MVM operation, the vast majority of SRMs have difficulty exhibiting the I-V linearity, which requires extra circuit compensation. [105] Current sensing is the primary readout scheme in IMC.…”

Section: Peripheral Circuitmentioning

confidence: 99%

Self‐Rectifying Memristors for Three‐Dimensional In‐Memory Computing

Ren,

Dong,

Yang

et al. 2023

Advanced Materials

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Costly data movement in terms of time and energy in traditional von Neumann systems is exacerbated by emerging information technologies related to artificial intelligence (AI). In‐memory computing (IMC) architecture aims to address this problem. Although the IMC hardware prototype represented by a memristor has developed rapidly and performs well, the sneak path issue is a critical and unavoidable challenge prevalent in large‐scale and high‐density crossbar arrays, particularly in three‐dimensional (3D) integration. As a perfect solution to the sneak‐path issue, self‐rectifying memristor (SRM) has been proposed for 3D integration because of its superior integration density. To date, SRMs have performed well in terms of power consumption (∼aJ) and scalability (> 102 Mbit). Moreover, SRM‐configured 3D integration is considered an ideal hardware platform for 3D IMC. This review focuses on the progress in SRMs and their applications in 3D memory, IMC, neuromorphic computing, and hardware security. The advantages, disadvantages, and optimization strategies of SRMs in diverse application scenarios are illustrated. Challenges posed by physical mechanisms, fabrication processes, and peripheral circuits, as well as potential solutions at the device and system levels, are also discussed.This article is protected by copyright. All rights reserved

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A Machine-Learning-Resistant 3D PUF with 8-layer Stacking Vertical RRAM and 0.014% Bit Error Rate Using In-Cell Stabilization Scheme for IoT Security Applications

Cited by 11 publications

References 7 publications

Sparse matrix multiplication in a record-low power self-rectifying memristor array for scientific computing

Sparse matrix multiplication in a record-low power self-rectifying memristor array for scientific computing

In-memory sparse matrix multiplication with a low-power self-rectifying memristor array

Self‐Rectifying Memristors for Three‐Dimensional In‐Memory Computing

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