A macro-layer level fully parallel layered LDPC decoder SOC for IEEE 802.15.3c application

Abstract

In this paper, we propose an ultra high-throughput LDPC decoder SOC to fulfill the requirement of IEEE 802.15.3c standard. By implementing a macro-layer fully parallel architecture, our proposed decoder takes only 4 clock cycles to finish one layered decoding iteration. Interconnection complexity problem introduced by highparallel decoding is nicely solved by proposed reusable message permutation networks utilizing the features of code PCM. Critical path is shortened by applying frame-level pipeline decoding. A 65nm CMOS chip is fabricated to verify the proposed architecture. Measured at 1.2V, 400MHz and 10 iterations the proposed decoder achieves a data throughput 6.72Gb/s and consumes a power 537.6mW with an energy efficiency 8.0 pJ/bitͼiter.

Efficient multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad applications

“…A CNU implements the operations shown in Eqs. (5) and (6). The detailed architecture of a pipelined CNU with dynamic column shifting and a local switch is shown in Fig.…”

“…A minimum sorter and sign processor implements Eq. (6). The structure of min-sorter is adopted from Wey et al [17].…”

“…To meet these demands, multi-gigabit data transmission rate standards, such as IEEE 802.11ad [2] for gigabit wireless local area networks (WLANs) and IEEE 802. 15.3c for wireless personal area networks (WPANs), have been proposed, which have necessitated the implementation of multi-gigabit high-throughput LDPC decoder architectures to meet the continuing demand for ever-higher data rates [5][6][7][8][9][10][11].…”

“…Yen et al [5] proposed an effective solution for reducing the routing and sorting congestion under 802.15.3c. Chen et al [6] proposed a further improvement and utilized the inherent block cyclic structure of 802. 15.3c LDPC code to develop an efficient decoder with fixed, wired switch networks.…”

“…w-1 w-1 mn1-a mn2-a sign[6] sign[5] sign[4] sign[3] sign[2] sign[1] sign[0]1 1 1 1 1 1 1 1 From Memory Distributor w-1 w-1 w-1 w-1 w-1 w-1 w-1 w-1 4 i-b sign[8] w-1 w-1 mn1-b mn2-b sign[9]sign[10] sign[11] sign[12] sign[13] sign[14] sign[15]1 1 1 1…”