A Majority-Based Imprecise Multiplier for Ultra-Efficient Approximate Image Multiplication

Sabetzadeh, Farnaz; Moaiyeri, Mohammad Hossein; Ahmadinejad, Mohammad

doi:10.1109/tcsi.2019.2918241

Cited by 142 publications

(117 citation statements)

References 34 publications

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“…Finally, we compare the proposed multiplier with the stateof-the-art multipliers based on inexact compressors [28], [32], [35], [36]. As these multipliers are 8-bit designs or implemented in FinFET technology, we compare them only in terms of PDP reductions and NMED reported in [28], [32], [35], [36]. Table 6 shows the reported NMED and PDP reduction for LOBO12−-12/8 the state-of-the-art multipliers based on inexact compressors.…”

Section: Synthesis Resultsmentioning

confidence: 99%

“…The proposed 4:2 and 5:2 compressors improve the power delay product (PDP), on average by 59% and 68%, and area by 60% and 75%, respectively. Sabetzadeh et al [36] adopted majority logic approximation to develop inexact compressors in Fin-FET technology. Compared to [35], the proposed compressor is designed with a smaller number of transistors and exhibits a lower error.…”

Section: B Approximate Non-logarithmic Multipliersmentioning

confidence: 99%

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On the Design of Logarithmic Multiplier Using Radix-4 Booth Encoding

Pilipović

Bulić

2020

IEEE Access

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This paper proposes an energy-efficient approximate multiplier which combines radix-4 Booth encoding and logarithmic product approximation. Additionally, a datapath pruning technique is proposed and studied to reduce the hardware complexity of the multiplier. Various experiments were conducted to evaluate the multiplier's error performance and efficiency in terms of energy and area utilization. The reported results are based on simulations using TSMC-180nm. Also, the applicability of the proposed multiplier is examined in image sharpening and convolutional neural networks. The applicability assessment shows that the proposed multiplier can replace an exact multiplier and deliver up to a 75% reduction in energy consumption and up to a 50% reduction in area utilization. Comparative analysis with the state-of-the-art multipliers indicates the potential of the proposed approach as a novel design strategy for approximate multipliers. When compared to the state-of-the-art approximate non-logarithmic multipliers, the proposed multiplier offers smaller energy consumption with the same level of applicability in image processing and classification applications. On the other hand, some state-of-the-art approximate logarithmic multipliers exhibit lower energy consumption than the proposed multiplier but deliver significant performance degradation for the selected application cases. INDEX TERMS Approximate computing, arithmetic circuit design, booth encoding, logarithmic multipliers, multipliers, power-efficient processing, truncated multipliers.

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Section: Synthesis Resultsmentioning

confidence: 99%

Section: B Approximate Non-logarithmic Multipliersmentioning

confidence: 99%

On the Design of Logarithmic Multiplier Using Radix-4 Booth Encoding

Pilipović

Bulić

2020

IEEE Access

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“…Ahmadinejad et al proposed two imprecise multipliers based on approximate 4:2 and 5:2 compressors, which can be implemented with 16 and 20 transistors 21 . Moreover, Sabetzadeh et al suggested an imprecise multiplier for image multiplication 2 . The majority logic‐based approximate compressor used in this multiplier is realized with 12 transistors.…”

Section: Backgroundsmentioning

confidence: 99%

“…However, miniaturization of the size of the CMOS transistors to compact the very large‐scale integration (VLSI chips) has imposed many serious concerns. These concerns such as drain‐induced barrier lowering (DIBL), high leakage currents, high power density, and reliability issues have restrained the functionality of the nanoscale circuits and systems 1,2 . Many solutions from the device level to the system level have been proposed to cope with these challenges.…”

Section: Introductionmentioning

confidence: 99%

Ultraefficient imprecise multipliers based on innovative 4:2 approximate compressors

Jooq

Ahmadinejad

Moaiyeri

2020

Circuit Theory & Apps

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SummaryThis study proposes two ultraefficient imprecise multipliers based on innovative 4:2 approximate compressor designs. The first proposed multiplier employs an ultracompact 8‐transistor 4:2 compressor to reduce the transistor count and energy dissipation. To improve the accuracy of the first proposed imprecise multiplier, the second multiplier also benefits from a semiaccurate 24‐transistor 4:2 approximate compressor for the high‐order bits. The 7‐nm fin field‐effect transistor (FinFET) technology, as one of the leading commercial technologies, is utilized to simulate the proposed multipliers in the environment. The simulation results indicate that the proposed imprecise multipliers show significant improvements regarding transistor count, delay, power, and power‐delay product as compared to their state‐of‐the‐art imprecise and exact counterparts. Along with the superior hardware efficiency, the MATLAB simulations demonstrate that the proposed multipliers also provide reasonable levels of accuracy. Moreover, a figure of merit (FOM) considering hardware efficiency and output quality is considered in order to evaluate the multipliers comprehensively. The FOM simulation results indicate that the proposed imprecise multipliers make a significant trade‐off between hardware efficiency and quality for approximate‐computing applications dealing with image multiplication.

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“…The limitations in CMOS technology such as high lithography, short channel effects, and power consumption encouraged scientists to think about alternatives. Many nanotechnologies were emerged to overcomes these limitations such as Single Electron Transistor [1,2], Carbon Nanotube Field-Effect Transistor [3][4][5][6][7], FinFET [8][9][10] and Quantum-dot Cellular Automata (QCA). QCA technology was introduced for the first time by Lent et al in 1993 [11] and it is reliability was studied in [12].…”

Section: Introductionmentioning

confidence: 99%

Novel Memory Structures in QCA Nano Technology

Majeed

Alkaldy²,

Zainal³

et al. 2020

IJEEE

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Quantum-dot Cellular Automata (QCA) is a new emerging technology for designing electronic circuits in nanoscale. QCA technology comes to overcome the CMOS limitation and to be a good alternative as it can work in ultra-high-speed. QCA brought researchers attention due to many features such as low power consumption, small feature size in addition to high frequency. Designing circuits in QCA technology with minimum costs such as cells count and the area is very important. This paper presents novel structures of D-latch and D-Flip Flop with the lower area and cell count. The proposed Flip-Flop has SET and RESET ability. The proposed latch and Flip-Flop have lower complexity compared with counterparts in terms of cell counts by 32% and 26% respectively. The proposed circuits are designed and simulated in QCADesigner software.

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A Majority-Based Imprecise Multiplier for Ultra-Efficient Approximate Image Multiplication

Cited by 142 publications

References 34 publications

On the Design of Logarithmic Multiplier Using Radix-4 Booth Encoding

On the Design of Logarithmic Multiplier Using Radix-4 Booth Encoding

Ultraefficient imprecise multipliers based on innovative 4:2 approximate compressors

Novel Memory Structures in QCA Nano Technology

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