A Markovian Queuing Model of a WLAN Node

Bylina, Jarosław; Bylina, Beata

doi:10.1007/978-3-642-21771-5_10

Cited by 7 publications

(6 citation statements)

References 2 publications

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“…Markovian queuing model [4] of such a mechanism is presented in Figure 1. The state of the model is described with four integers (c, k, f, s):…”

Section: Wlan Node Modelmentioning

confidence: 99%

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Computational Aspects of GPU-accelerated Sparse Matrix-Vector Multiplication for Solving Markov Models

Bylina

Karwacki³

2011

Theoretical and Applied Informatics

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In this article we investigate some computational aspects of GPU-accelerated matrix-vector multiplication where matrix is sparse. Particularly, we deal with sparse matrices appearing in modelling with Markovian queuing models. The model we use for research is a Markovian queuing model of a wireless device. This model describes the device's behavior during possible channel occupation by other devices.We study the efficiency of multiplication of a sparse matrix by a dense vector with the use of an appropriate, ready-to-use GPU-accelerated mathematical library, namely CUSP. For the CUSP library we discuss data structures and their impact on the CUDA platform for the fine-grained parallel architecture of the GPU. Our aim is to find the best format for storing a sparse matrix for GPU-computation (especially one associated with the Markovian model of a wireless device).We compare the time, the performance and the speed-up for the card NVIDIA Tesla C2050 (with ECC ON). For unstructured matrices (as our Markovian matrices), we observe speed-ups (in respect to CPU-only computations) of over 8 times.

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“…Markovian queuing model [4] of such a mechanism is presented in Figure 1. The state of the model is described with four integers (c, k, f, s):…”

Section: Wlan Node Modelmentioning

confidence: 99%

“…Recently they are commonly used for modelling wireless networks [3,4,10]. One of the problems appearing while using Markov chains to model complex systems making difficult the full utilization of the approach is a very large size of the model and thereby implied a long computation time (and memory consumption).…”

Section: Introductionmentioning

confidence: 99%

Computational Aspects of GPU-accelerated Sparse Matrix-Vector Multiplication for Solving Markov Models

Bylina

Karwacki³

2011

Theoretical and Applied Informatics

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“…Sparse Linear algebra is vital to scientific computations and various fields of engineering and thus has been included among the seven dwarfs [1] by the Berkeley researchers. Among the sparse numerical techniques, iterative solutions of sparse linear equation systems can be considered as of prime importance due to its application in various important areas such as solving finite differences of partial differential equations (PDEs) [2][3][4], high accuracy surface modelling [5], finding steady-state and transient solutions of Markov chains [6][7][8], probabilistic model checking [9][10][11], solving the time-fractional Schrödinger equation [12], web ranking [13][14][15], inventory control and manufacturing systems [16], queuing systems [17][18][19][20][21][22][23], fault modelling, weather forecasting, stochastic automata networks [24,25], communication systems and networks [26][27][28][29][30][31], reliability analysis [32], wireless and sensor networks [33][34][35][36][37], computational biology [38], healthcare [27,39,40], transportation [41,…”

Section: Introductionmentioning

confidence: 99%

SURAA: A Novel Method and Tool for Loadbalanced and Coalesced SpMV Computations on GPUs

et al. 2019

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Sparse matrix-vector (SpMV) multiplication is a vital building block for numerous scientific and engineering applications. This paper proposes SURAA (translates to speed in arabic), a novel method for SpMV computations on graphics processing units (GPUs). The novelty lies in the way we group matrix rows into different segments, and adaptively schedule various segments to different types of kernels. The sparse matrix data structure is created by sorting the rows of the matrix on the basis of the nonzero elements per row ( n p r) and forming segments of equal size (containing approximately an equal number of nonzero elements per row) using the Freedman–Diaconis rule. The segments are assembled into three groups based on the mean n p r of the segments. For each group, we use multiple kernels to execute the group segments on different streams. Hence, the number of threads to execute each segment is adaptively chosen. Dynamic Parallelism available in Nvidia GPUs is utilized to execute the group containing segments with the largest mean n p r, providing improved load balancing and coalesced memory access, and hence more efficient SpMV computations on GPUs. Therefore, SURAA minimizes the adverse effects of the n p r variance by uniformly distributing the load using equal sized segments. We implement the SURAA method as a tool and compare its performance with the de facto best commercial (cuSPARSE) and open source (CUSP, MAGMA) tools using widely used benchmarks comprising 26 high n p r v a r i a n c e matrices from 13 diverse domains. SURAA outperforms the other tools by delivering 13.99x speedup on average. We believe that our approach provides a fundamental shift in addressing SpMV related challenges on GPUs including coalesced memory access, thread divergence, and load balancing, and is set to open new avenues for further improving SpMV performance in the future.

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“…Examples of complex systems considered in this article are call centers [14,27,33] and wireless networks [3,8,9]. For large matrices (and such matrices arise during modeling complex system), the methods based on numerical solving of ordinal differential equations are the most useful [4,17,28,31].…”

Section: Introductionmentioning

confidence: 99%

Explicit Fourth-Order Runge–Kutta Method on Intel Xeon Phi Coprocessor

Bylina

Potiopa

2016

Int J Parallel Prog

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This paper concerns an Intel Xeon Phi implementation of the explicit fourthorder Runge-Kutta method (RK4) for very sparse matrices with very short rows. Such matrices arise during Markovian modeling of computer and telecommunication networks. In this work an implementation based on Intel Math Kernel Library (Intel MKL) routines and the authors' own implementation, both using the CSR storage scheme and working on Intel Xeon Phi, were investigated. The implementation based on the Intel MKL library uses the high-performance BLAS and Sparse BLAS routines. In our application we focus on OpenMP style programming. We implement SpMV operation and vector addition using the basic optimizing techniques and the vectorization. We evaluate our approach in native and offload modes for various number of cores and thread allocation affinities. Both implementations (based on Intel MKL and made by the authors) were compared in respect of the time, the speedup and the performance. The numerical experiments on Intel Xeon Phi show that the performance of authors' implementation is very promising and gives a gain of up to two times compared to the multithreaded implementation (based on Intel MKL) running on CPU (Intel Xeon processor) and even three times in comparison with the application which uses Intel MKL on Intel Xeon Phi.The authors are grateful to Czestochowa University of Technology for granting access to Intel CPU and Intel Xeon Phi platforms providing by the MICLAB

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A Markovian Queuing Model of a WLAN Node

Cited by 7 publications

References 2 publications

Computational Aspects of GPU-accelerated Sparse Matrix-Vector Multiplication for Solving Markov Models

Computational Aspects of GPU-accelerated Sparse Matrix-Vector Multiplication for Solving Markov Models

SURAA: A Novel Method and Tool for Loadbalanced and Coalesced SpMV Computations on GPUs

Explicit Fourth-Order Runge–Kutta Method on Intel Xeon Phi Coprocessor

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