A massively scalable Time-to-Digital Converter with a PLL-free calibration system in a commercial 130 nm process

Abstract

A 33.6 ps LSB Time-to-Digital converter was designed in 130 nm BiCMOS technology. The core of the converter is a differential 9-stage ring oscillator, based on a multi-path architecture. A novel version of this design is proposed, along with an analytical model of linearity. The model allowed us to understand the source of the performance superiority (in terms of linearity) of our design and to predict further improvements. The oscillator is integrated in a event-by-event self-calibration system that allows avoiding any PLL-based synchronization. For this reason and for the compactness and simplicity of the architecture, the proposed TDC is suitable for applications in which a large number of converters and a massive parallelization are required such as High-Energy Physics and medical imaging detector systems. A test chip for the TDC has been fabricated and tested. The TDC shows a DNL≤1.3 LSB, an INL≤2 LSB and a single-shot precision of 19.5 ps (0.58 LSB). The chip dissipates a power of 5.4 mW overall.

Efficiency and time resolution of monolithic silicon pixel detectors in SiGe BiCMOS technology

“…The fast-or lines are interleaved so that two adjacent pixels are always connected to separate TDCs: this ensures that in the event of a particle hitting multiple adjacent pixels, the timing information can be measured from all of them independently. The TDC architecture is described in [13]. A 9-stage pseudo-nMOS feed-forward ring oscillator is used with a set of latches to sample the oscillator state.…”

Efficiency and time resolution of monolithic silicon pixel detectors in SiGe BiCMOS technology

“…The fast-or lines are interleaved so that two adjacent pixels are always connected to separate TDCs: this ensures that in the event of a particle hitting multiple adjacent pixels, the timing information can be measured from all of them independently. The TDC architecture is described in [11]. A 9-stage pseudo-nMOS feed-forward ring oscillator is used with a set of latches to sample the oscillator state.…”

A 1.9 ps-rms Precision Time-to-Amplitude Converter With 782 fs LSB and 0.79%-rms DNL

“…Two architectures are mostly used to design timing circuits: time-to-digital converters (TDCs) and time-to-amplitude converters (TACs) followed by an ADC. On the one hand, TDCs can be more compact [15], [16], [17], [18], they can be implemented directly in FPGAs [19], [20], [21], and have recently gained popularity also as part of digital phase-locked loops (PLLs) [22], [23], [24], but with different requirements with respect to light detection and ranging (LiDAR) and biological applications [e.g., PLLs typically require sub-ns full-scale ranges (FSR)]. On the other hand, TAC-based architectures have been the solution of choice so far in high-demanding applications, particularly in lifetime analysis, thanks to their superior linearity that can be combined with picoseconds timing precision on the whole nanoseconds FSR, and high scalability resorting to application-specific integrated circuits (ASICs).…”