A Memetic Approach for Nanoscale Hybrid Circuit Cell Mapping

Chu, Zhufei; Xia, Yinshui; Hung, William N. N.; Wang, Lunyao; Song, Xiaoyu

doi:10.1109/dsd.2010.22

Cited by 10 publications

(12 citation statements)

References 20 publications

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“…Results for defect scenario (i) are given in the following tables; Table 3 report the maximum and averaged CPU computation times (in seconds), which SimE and TS needed to reconfigure all benchmark circuits for random and clustered defect maps when q nano is between 10 and 30 %. For this given range of stuck-open probabilities, both SimE and TS were successful in reconfiguring circuits around all defective 1 Previous solutions for CMOL cells placement [21,[23][24][25][26]28] defined the connectivity domain based on Manhattan distance, where a cell is said to be within the connectivity domain of another cell if the Manhattan distance between them is less or equal to connectivity radius a = 12.…”

Section: Reconfiguration Resultsmentioning

confidence: 99%

“…3 proposals had been introduced for defect-unaware cell placement/assignment in CMOL circuits including the works of Likharev et al [15,22] and Hung et al [23]. Previous attempts to use sub-optimal search heuristics for CMOL placement are reported in [24][25][26][27]. Simulated evolution [28] and TS [21,29] heuristics have also been attempted for defect-unaware CMOL placement problem.…”

Section: Literature Reviewmentioning

confidence: 98%

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Reconfiguration-Based Defect-Tolerant Design Automation for Hybrid CMOS/Nanofabrics Circuits Using Evolutionary and Non-Deterministic Heuristics

Sait

Arafeh

2015

Arab J Sci Eng

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Recently, a shift from CMOS lithography to nanoelectronics chemical assembly has been under investigation. Nanoscale components are assembled into arrays of low-power and high-density nanofabrics, which can be integrated with conventional CMOS systems. The inability to achieve inexpensive defect-free mass manufacturing of nanoelectronics is the largest impediment of their adoption. Limited nanowire lengths and defect-prone nanodevices pose significant challenges for design automation tools. In this work, we propose a design phase for cell mapping and reconfiguration in novel hybrid CMOS/nanoelectronics architecture called CMOL. Reconfiguration consists of finding new suitable physical location for each gate such that the circuit becomes defect free. The novelty of this work is to engineer non-deterministic iterative search heuristics, namely simulated evolution (SimE) and Tabu search (TS), to find cell assignment around defective nano-components. Circuits of various sizes from ISCAS'89 benchmarks are used to evaluate the designed heuristics. Results show that SimE and TS yield successful reconfigurations in reasonable computation time when nanodevice defect rate is as high as 50 % and nanowire cut rate up to 70 %.

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Section: Reconfiguration Resultsmentioning

confidence: 99%

Section: Literature Reviewmentioning

confidence: 98%

Reconfiguration-Based Defect-Tolerant Design Automation for Hybrid CMOS/Nanofabrics Circuits Using Evolutionary and Non-Deterministic Heuristics

Sait

Arafeh

2015

Arab J Sci Eng

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“…The main difference between works in [23] and this paper is the integration of LRT within the MA framework. By moving the hard structural connectivity domain constraint to the cost function, a Lagrangian problem is formulated and solved by the MA incremental search engine.…”

Section: A Overviewmentioning

confidence: 94%

“…A preliminary conference version of our work [23] presented a basic framework of MA for CMOL cell mapping. In this paper, we extend our work and formulate it as an LR problem by moving hard connectivity domain constraints to the objective function.…”

Section: Introductionmentioning

confidence: 99%

An Integrated Optimization Approach for Nanohybrid Circuit Cell Mapping

Xia

Chu

Hung

et al. 2011

IEEE Trans. Nanotechnology

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This paper presents an integrated optimization approach for nanohybrid circuit (CMOS/nanowire/molecular hybrid) cell mapping. The method integrates Lagrangian relaxation and memetic search synergistically. Based on encoding manipulation with appropriate population and structural connectivity constraints, 2-D block crossover, mutation, and self-learning operators are developed in a concerted way to obtain an effective mapping solution. In addition, operative buffer insertion is performed to leverage the quality of routing. Numerical results from ISCAS benchmarks and comparison with previous methods demonstrate the effectiveness of the modeling and solution methodology. The method outperforms the previous work in terms of CPU runtime, timing delay, and circuit scale.

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“…Instead of working at tiles level, Hung et al [6] encoded the CMOL cell assignment as a Satisfiability problem at cells level, where placement solution was found when all Boolean constraints are satisfied. However, when circuits sizes increased the computation time became exhibitant Previous attempts to use sub-optimal search heuristics are reported in [7,8,9]. Genetic Algorithm (GA) [7] was used with two dimensional block PMX crossover operator and mutation, where the fitness function evaluates the Manhattan distance between connected cells.…”

Section: Introductionmentioning

confidence: 99%

Efficient CMOL nanoscale hybrid circuit cell assignment using simulated evolution heuristic

Sait

Arafeh

2012

Proceedings of the Great Lakes Symposium on VLSI

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Recently, many CMOS/nanodevices hybrid architectures have been proposed, the new architectures combine the flexibility and high fabrication yield advantages of CMOS technology with nanometer scale latching devices. CMOL, a novel architecture that uses two levels of perpendicular nanowires as crossbar interconnection on top of inverter-based CMOS stack, offers significant density advantages and overcomes physical barriers of lithography-based fabrication. However, the confined connectivity of CMOL nanofabric to only cells that are located within proximity square-like connectivity domain, reduces the flexibility of VLSI design automation and further complicates cells placement.In this paper we use Simulated Evolution algorithm to solve the NP-hard problem of assigning NOR/INV gates to CMOL array. The main objective is to reduce the total number of buffers that must be inserted between cells that require long wires to connect. A novel goodness and allocation functions are introduced for efficient exploration of search space. Empirical results for ISCAS'89 benchmarks are compared with previous solutions using GA, MA, and LRMA heuristics. Our approach is able to find better solutions for all tested benchmarks and with 82% average reduction in CPU processing time.

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A Memetic Approach for Nanoscale Hybrid Circuit Cell Mapping

Cited by 10 publications

References 20 publications

Reconfiguration-Based Defect-Tolerant Design Automation for Hybrid CMOS/Nanofabrics Circuits Using Evolutionary and Non-Deterministic Heuristics

Reconfiguration-Based Defect-Tolerant Design Automation for Hybrid CMOS/Nanofabrics Circuits Using Evolutionary and Non-Deterministic Heuristics

An Integrated Optimization Approach for Nanohybrid Circuit Cell Mapping

Efficient CMOL nanoscale hybrid circuit cell assignment using simulated evolution heuristic

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