No abstract

Recently, many CMOS/nanodevices hybrid architectures have been proposed, the new architectures combine the flexibility and high fabrication yield advantages of CMOS technology with nanometer scale latching devices. CMOL, a novel architecture that uses two levels of perpendicular nanowires as crossbar interconnection on top of inverter-based CMOS stack, offers significant density advantages and overcomes physical barriers of lithography-based fabrication. However, the confined connectivity of CMOL nanofabric to only cells that are located within proximity square-like connectivity domain, reduces the flexibility of VLSI design automation and further complicates cells placement.In this paper we use Simulated Evolution algorithm to solve the NP-hard problem of assigning NOR/INV gates to CMOL array. The main objective is to reduce the total number of buffers that must be inserted between cells that require long wires to connect. A novel goodness and allocation functions are introduced for efficient exploration of search space. Empirical results for ISCAS'89 benchmarks are compared with previous solutions using GA, MA, and LRMA heuristics. Our approach is able to find better solutions for all tested benchmarks and with 82% average reduction in CPU processing time.

In this paper we describe the engineering of a non-deterministic iterative heuristic [1] known as simulated evolution(SimE) to solve the well-known NP-hard state assignment problem (SAP). Each assignment of a code to a state isgiven a Goodness value derived from a matrix representation of the desired adjacency graph (DAG) proposed byAmaral et.al [2]. We use the (DAGa) proposed in previous studies to optimize the area, and propose a new DAGpand employ it to reduce the power dissipation. In the process of evolution, those states that have high Goodness havea smaller probability of getting perturbed, while those with lower Goodness can be easily reallocated. States areassigned to cells of a Karnaugh-map, in a way that those states that have to be close in terms of Hamming distanceare assigned adjacent cells. Ordered weighed average (OWA) operator proposed by Yager [3] is used to combine thetwo objectives. Results are compared with those published in previous studies, for circuits obtained from the MCNCbenchmark suite. It was found that the SimE heuristic produces better quality results in most cases, and/or in lessertime, when compared to both deterministic heuristics and non-deterministic iterative heuristics such as GeneticAlgorithm.

Recently, a shift from CMOS lithography to nanoelectronics chemical assembly has been under investigation. Nanoscale components are assembled into arrays of low-power and high-density nanofabrics, which can be integrated with conventional CMOS systems. The inability to achieve inexpensive defect-free mass manufacturing of nanoelectronics is the largest impediment of their adoption. Limited nanowire lengths and defect-prone nanodevices pose significant challenges for design automation tools. In this work, we propose a design phase for cell mapping and reconfiguration in novel hybrid CMOS/nanoelectronics architecture called CMOL. Reconfiguration consists of finding new suitable physical location for each gate such that the circuit becomes defect free. The novelty of this work is to engineer non-deterministic iterative search heuristics, namely simulated evolution (SimE) and Tabu search (TS), to find cell assignment around defective nano-components. Circuits of various sizes from ISCAS'89 benchmarks are used to evaluate the designed heuristics. Results show that SimE and TS yield successful reconfigurations in reasonable computation time when nanodevice defect rate is as high as 50 % and nanowire cut rate up to 70 %.

Recent advances in nanoscale components assembly have led to the invention of low-power and highdensity nanofabrics, which can be integrated with conventional CMOS transistors. CMOS/nanofabric hybrid circuits combine the flexibility and high fabrication yield advantages of CMOS technology with ultra fast nanometerscale devices. CMOL is a novel architecture which consists of a nanofabric overlay on top of a CMOS stack. CMOL can be configured to implement NOR-based logic circuits by programming nanodevices placed between the nanofabric's overlapping nanowires. Defects rate in nanofabric-based circuits is expected to be higher than that of conventional CMOS technology. Misassembly of nanodevices will lead to non-programmable crosspoints, while broken nanowires will result in unreachable circuit's components. In such cases, utilizing CMOS/nanofabric architectures requires robust reconfiguration-based defect-tolerance design automation tools that can circumvent defective components and insure circuits functionality.In this work, we propose a heuristic-based nanofabric reconfiguration around defective nano-components in CMOL circuits. Simulated Evolution (SimE) is formulated to find circuits configurations that adhere to nanowires connectivity constraint and rely on non defective components. Circuits of various sizes from ISCAS'89 benchmarks were used to evaluate our proposed design. Results show that SimE yield successful reconfigurations in acceptable computation time when up to 50% of nanodevices are stuck-at-open and 70% of nanowires are broken.