A Memory Efficient, High Throughput and Fastest 1D/3D VLSI Architecture for Reconfigurable 9/7 & 5/3 DWT Filters

Efficient VLSI architectures of lifting based 3D discrete wavelet transform

“…In 3D‐DWT architecture, the first processing unit is row processor that will accept the frames of 3D‐input. The number of row processors in (5,3) 3D‐DWT of [10], four‐tap Daubechies 3D‐DWT of [11], (5,3) 3D‐DWT of [12], (9,7) 3D‐DWT of [13], (9,7) 3D‐DWT of [14], (9,7) 3D‐DWT of [15], (9,7) 3D‐DWT of [16], (9,7) 3D‐DWT of [17], proposed (5,3) 3D‐DWT, and proposed (9,7) 3D‐DWT are 1, 2, 5, 1, 1, 2, 4, 4, 25, and 81, respectively. Similarly, the number of frames that can be accepted per cycle by all the row processors in (5,3) 3D‐DWT of [10], four‐tap Daubchies 3D‐DWT of [11], (5,3) 3D‐DWT of [12], (9,7) 3D‐DWT of [13], (9,7) 3D‐DWT of [14], (9,7) 3D‐DWT of [15], (9,7) 3D‐DWT of [16], (9,7) 3D‐DWT of [17], proposed (5,3) 3D‐DWT, and proposed (9,7) 3D‐DWT are 1, 2, 5, 1, 1, 2, 2, 4, 5, and 9, respectively.…”

“…The number of row processors in (5,3) 3D‐DWT of [10], four‐tap Daubechies 3D‐DWT of [11], (5,3) 3D‐DWT of [12], (9,7) 3D‐DWT of [13], (9,7) 3D‐DWT of [14], (9,7) 3D‐DWT of [15], (9,7) 3D‐DWT of [16], (9,7) 3D‐DWT of [17], proposed (5,3) 3D‐DWT, and proposed (9,7) 3D‐DWT are 1, 2, 5, 1, 1, 2, 4, 4, 25, and 81, respectively. Similarly, the number of frames that can be accepted per cycle by all the row processors in (5,3) 3D‐DWT of [10], four‐tap Daubchies 3D‐DWT of [11], (5,3) 3D‐DWT of [12], (9,7) 3D‐DWT of [13], (9,7) 3D‐DWT of [14], (9,7) 3D‐DWT of [15], (9,7) 3D‐DWT of [16], (9,7) 3D‐DWT of [17], proposed (5,3) 3D‐DWT, and proposed (9,7) 3D‐DWT are 1, 2, 5, 1, 1, 2, 2, 4, 5, and 9, respectively. The total number of input samples values () that can be processed per cycle by all the row processors in (5,3) 3D‐DWT of [10], four‐tap Daubchies 3D‐DWT of [11], (5,3) 3D‐DWT of [12], (9,7) 3D‐DWT of [13], (9,7) 3D‐DWT of [14], (9,7) 3D‐DWT of [15], (9,7) 3D‐DWT of [16], (9,7) 3D‐DWT of [17], proposed (5,3) 3D‐DWT, and proposed (9,7) 3D‐DWT are (), (), (), (), (), (), (), (), (), and (), respectively.…”

“…Our proposed architectures need one FMA and an adder in the critical path. Therefore, the critical path delay of our proposed designs is much less than the existing designs [10, 12, 15, 16], because these existing techniques need two adders and one multiplier in their critical path. Also, the critical path of four‐tap Daubechies 3D‐DWT as shown in [11] requires more than four adders.…”

“…Hence, the throughput of [15] is greater than [13]. A memory efficient lifting based 3D‐DWT is shown in [16], where four numbers of row processors, four numbers of column processors, and one temporal processor are used. Also, this design is flexible to perform both (5,3) and (9,7) filter operations.…”