A memory grouping method for sharing memory bist logic

Miyazaki,; Yoneda,; Fujiwara,

doi:10.1109/aspdac.2006.1594763

Cited by 22 publications

(8 citation statements)

References 5 publications

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“…Memories are grouped based on their logical hierarchies, their physical locations, and access types. In BIST Share [MYF+06], the authors consider all aspects of BIST cost and present an algorithm to minimize the BIST area under time and power constraints.…”

Section: Previous Workmentioning

confidence: 99%

Layout-Aware and Programmable Memory BIST Synthesis for Nanoscale System-on-Chip Designs

Kokrady

Ravikumar

Chandrachoodan

2008

2008 17th Asian Test Symposium

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Debugging memory test failures in a system-on-chip design is becoming difficult due to the growing number and sizes of the embedded memories. Low-complexity marching tests, which are ideally suited for production testing, are insufficient for debug and diagnostics. On-chip support for multiple memory test algorithms can be prohibitively expensive. Moreover, memory test engineers would like the flexibility to make small changes to the test sequence. Runtime programmability can be provided through the use of programmable finite state machines and/or microcode in the BIST controllers. Since such controllers have higher area requirement, it is difficult to employ multiple controllers and distribute them geographically on the chip. Therefore, the BIST controller can become a routing hot-spot. Existing memory BIST insertion flows operate on a post-synthesis net-list and ignore the constraints that will be posed by the physical design step that will follow. These constraints include routing congestion and interconnect timing. Similarly, the synthesis of the BIST logic must also address area, test application time and test power constraints. In this paper, we formulate the problem of programmable memory BIST synthesis as an optimization problem and describe an implementation. Results show upto 3X improvement in area and wirelength for industrial designs when a layout-aware flow is used as opposed to manual BIST implementation.

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Section: Previous Workmentioning

confidence: 99%

Layout-Aware and Programmable Memory BIST Synthesis for Nanoscale System-on-Chip Designs

Kokrady

Ravikumar

Chandrachoodan

2008

2008 17th Asian Test Symposium

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“…To our knowledge, relatively few works exist in the realm of (physically-aware) design optimization of memory BIST. 2 A memory grouping method for sharing memory BIST logic is proposed by Miyazaki et al in [17]. Area overhead reductions are achieved by the grouping of memories for parallel and serial testing.…”

Section: B Design Optimizations For Memory Bist Controllersmentioning

confidence: 99%

“…We assume that a memory has test time proportional to its depth [17] and test power proportional to the square root of its size. Based on our studies, we see that allowing both serial and parallel testing of memories can reduce test time as illustrated in Figure 1.…”

Section: Ilp Formulationmentioning

confidence: 99%

Co-optimization of memory BIST grouping, test scheduling, and logic placement

Kahng

Kang

2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-Built-in self-test (BIST) is a well-known design technique in which part of a circuit is used to test the circuit itself. BIST plays an important role for embedded memories, which do not have pins or pads exposed toward the periphery of the chip for testing with automatic test equipment. With the rapidly increasing number of embedded memories in modern SOCs (up to hundreds of memories in each hard macro of the SOC), product designers incur substantial costs of test time (subject to possible power constraints) and BIST logic physical resources (area, routing, power). However, only limited previous work addresses the physical design optimization of BIST logic; notably, Chien et al. [7] optimize BIST design with respect to test time, routing length, and area. In our work, we propose a new three-step heuristic approach to minimize test time as well as test physical layout resources, subject to given upper bounds on power consumption. A key contribution is an integer linear programming ILP framework that determines optimal test time for a given cluster of memories using either one or two BIST controllers, subject to test power limits and with full comprehension of available serialization and parallelization. Our heuristic approach integrates (i) generation of a hypergraph over the memories, with test time-aware weighting of hyperedges, along with top-down, FM-style min-cut partitioning; (ii) solution of an ILP that comprehends parallel and serial testing to optimize test scheduling per BIST controller; and (iii) placement of BIST logic to minimize routing and buffering costs. When evaluated on hard macros from a recent industrial 28nm networking SOC, our heuristic solutions reduce test time estimates by up to 11.57% with strictly fewer BIST controllers per hard macro, compared to the industrial solutions.

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“…For each single memory (or a memory group [10]), spare rows, spare column group blocks, and spare words are added for replacing faulty cells. Based on the redundancy mechanism, a BISR scheme suitable for built-in implementation is proposed.…”

Section: Introductionmentioning

confidence: 99%

Wireless built-in self-repair architectures for embedded RAMs

Wang

Tsai

Hsiao

et al. 2009

2009 IEEE 8th International Conference on ASIC

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In order to reduce test and repair cost in advanced system-on-chip products, wireless built-in self-repair (BISR) techniques for embedded memories are proposed in this paper. The redundant memory is divided into spare rows, spare column group blocks, and spare words which are used to replace faulty cells in the main memory. Based on this redundancy architecture, a BISR scheme suitable for built-in implementation is proposed. According to simulation results, our techniques have higher repair rates and lower hardware overhead as compared with previous works. Finally, we integrated the proposed memory with BISR circuitry into the HOY wireless test system. Experimental results show that the hardware overhead (including the wireless interface modules) is only O.39%for a 16 M-bit SRAM

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A memory grouping method for sharing memory bist logic

Cited by 22 publications

References 5 publications

Layout-Aware and Programmable Memory BIST Synthesis for Nanoscale System-on-Chip Designs

Layout-Aware and Programmable Memory BIST Synthesis for Nanoscale System-on-Chip Designs

Co-optimization of memory BIST grouping, test scheduling, and logic placement

Wireless built-in self-repair architectures for embedded RAMs

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