ATPG tools generate test vectors assuming zero delay model for logic gates. In reality, however, gates have finite rise and fall delays that are dependent on process, voltage, and temperature variations across different dies on a wafer and within a die. A test engineer must verify the vectors for timing correctness before they are handed off to the product engineer. Currently, validation of tests is done using dynamic simulation of the circuit using the test vectors. A test vector is invalidated if it cannot reliably distinguish between a good and a faulty circuit under the signal placement and observation error window of the tester equipment. Since structural tests can result in much more switching activity in the circuit than what is estimated during normal functioning, the IR drop in the power & ground lines can be significant, adversely impacting path delays. As a result, the validation performed by simulation can be error prone. Oversizing the power rails to address this problem impacts the yield. We therefore propose the verification of test vectors for IR drop failure and present a flow for identifying failing vectors. Attempting to address this verification in dynamic simulation will force the use of circuit simulation or mixed-level simulation techniques, which are expensive in terms of run time. We discuss a static approach to validate the test vectors for failure in the presence of IR drop problems.

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Debugging memory test failures in a system-on-chip design is becoming difficult due to the growing number and sizes of the embedded memories. Low-complexity marching tests, which are ideally suited for production testing, are insufficient for debug and diagnostics. On-chip support for multiple memory test algorithms can be prohibitively expensive. Moreover, memory test engineers would like the flexibility to make small changes to the test sequence. Runtime programmability can be provided through the use of programmable finite state machines and/or microcode in the BIST controllers. Since such controllers have higher area requirement, it is difficult to employ multiple controllers and distribute them geographically on the chip. Therefore, the BIST controller can become a routing hot-spot. Existing memory BIST insertion flows operate on a post-synthesis net-list and ignore the constraints that will be posed by the physical design step that will follow. These constraints include routing congestion and interconnect timing. Similarly, the synthesis of the BIST logic must also address area, test application time and test power constraints. In this paper, we formulate the problem of programmable memory BIST synthesis as an optimization problem and describe an implementation. Results show upto 3X improvement in area and wirelength for industrial designs when a layout-aware flow is used as opposed to manual BIST implementation.

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