Fast, layout-aware validation of test-vectors for nanometer-related timing failures

Kokrady, A.; Ravikumar, C.P.

doi:10.1109/icvd.2004.1260984

Cited by 19 publications

(5 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In [3], a pattern generation technique was proposed to create maximum supply noise to increase the delay along targeted paths. There has also been a pattern postprocessing technique to verify patterns that cause excessive IR-drop [4]. Neural network and genetic algorithm based solutions were proposed in [5].…”

Section: A Related Workmentioning

confidence: 99%

Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation

Lee¹,

Narayan²,

Kapralos³

et al. 2008

2008 Design, Automation and Test in Europe

View full text Add to dashboard Cite

Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shipped to the customers fault-free. However, at-speed tests have been known to create higher-than-average switching activity, which normally is not accounted for in the design of the power supply network. This potentially creates conditions for additional delay in the chip; causing it to fail during test. In this paper, we propose a pattern compaction technique that considers the layout and gate distribution when generating transition delay fault patterns. The technique focuses on evenly distributing switching activity generated by the patterns across the layout rather than allowing high switching activity to occur in a small area in the chip that could occur with conventional delay fault pattern generation. Due to the relationship between switching activity and IR-drop, the reduction of switching will prevent large IR-drop in high demand regions while still allowing a suitable amount of switching to occur elsewhere on the chip to prevent fault coverage loss. This even distribution of switching on the chip will also result in avoiding hot-spots.

show abstract

Section: A Related Workmentioning

confidence: 99%

Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation

Lee¹,

Narayan²,

Kapralos³

et al. 2008

2008 Design, Automation and Test in Europe

View full text Add to dashboard Cite

show abstract

“…[8][9][10] A pattern post-processing technique (i.e., pattern validation) to verify TDF patterns that cause excessive IR-drop was proposed in Ref. [7]. Attempting to address this verification in dynamic simulation will force the use of circuit simulation or mixed-level simulation techniques, which are expensive in terms of run time.…”

Section: Related Workmentioning

confidence: 99%

Layout-Aware Transition-Delay Fault Pattern Generation with Evenly Distributed Switching Activity

Lee¹,

Tehranipoor²

2008

Journal of Low Power Electronics

View full text Add to dashboard Cite

As chip integration continues to increase and technology scaling is forcing the operating voltage to decrease, modern designs have become more susceptible to supply voltage noise. However, even with a well designed power distribution network, modern at-speed test pattern generation techniques do not consider the maximum current throughput the network will be able to provide. As a result, conventional transition delay fault pattern generation tends to create a number of patterns that cause higher-than-average functional switching, which may cause timing and/or functional failures during test. In this paper, we propose a flow that incorporates the layout information and the locality of the switching activity during pattern generation to provide insight into the amount of tolerable switching. This will prevent both IR-drop related hot-spots and under-utilization of the chip since the switching activity can be evenly spread across the design. The results presented in this paper show significant improvement over our previous flow without negatively impacting fault coverage and pattern count.

show abstract

“…Since this results in power-supply-noise-induced yield loss, power supply noise has become a critical issue in high-quality atspeed scan testing [14,15].…”

Section: Power Supply Noisementioning

confidence: 99%

“…Approximation methods [10,14,15] are often used since accurate analysis is time-consuming. Their results are used to guide test generation [14] or reduce the number of target test vectors before accurate analysis is conducted for sign-off [15].…”

Section: Power Supply Noisementioning

confidence: 99%

A novel scheme to reduce power supply noise for high-quality at-speed scan testing

Wen

Miyase

Kajihara

et al. 2007

2007 IEEE International Test Conference

View full text Add to dashboard Cite

High-quality at-speed scan testing, characterized by high small-delay-defect detecting capability, is indispensable to achieve high delay test quality for DSM circuits. However, such testing is susceptible to yield loss due to excessive power supply noise caused by high launch-induced switching activity. This paper addresses this serious problem with a novel and practical post-ATPG X-filling scheme, featuring (1) (JP-fill), that is both effective and scalable for reducing launch-induced switching activity. This scheme can be easily implemented into any ATPG flow to effectively reduce power supply noise, without any impact on delay test quality, test data volume, area overhead, and circuit timing. a test relaxation method, called path keeping X-identification, that finds don't-care bits from a fully-specified transition delay test set while preserving its delay test quality by keeping the longest paths originally sensitized for fault detection, and (2) an X-filling method, called justification-probability-based fillPaper 25.1

show abstract

Fast, layout-aware validation of test-vectors for nanometer-related timing failures

Cited by 19 publications

References 9 publications

Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation

Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation

Layout-Aware Transition-Delay Fault Pattern Generation with Evenly Distributed Switching Activity

A novel scheme to reduce power supply noise for high-quality at-speed scan testing

Contact Info

Product

Resources

About