A novel scheme to reduce power supply noise for high-quality at-speed scan testing

Abstract

High-quality at-speed scan testing, characterized by high small-delay-defect detecting capability, is indispensable to achieve high delay test quality for DSM circuits. However, such testing is susceptible to yield loss due to excessive power supply noise caused by high launch-induced switching activity. This paper addresses this serious problem with a novel and practical post-ATPG X-filling scheme, featuring (1) (JP-fill), that is both effective and scalable for reducing launch-induced switching activity. This scheme can be easily implemented into any ATPG flow to effectively reduce power supply noise, without any impact on delay test quality, test data volume, area overhead, and circuit timing. a test relaxation method, called path keeping X-identification, that finds don't-care bits from a fully-specified transition delay test set while preserving its delay test quality by keeping the longest paths originally sensitized for fault detection, and (2) an X-filling method, called justification-probability-based fillPaper 25.1

A novel X-filling method for capture power reduction

“…This paper proposes a X-filling method to reduce the capture power. Several X-filling methods have been studied to reduce capture power by controlling X-bits [6,7,8,9,10]. Justification based X-filling methods were proposed in [6,7].…”

“…However, to calculate the probability, the accurate structure of the circuit under test is needed. Therefore, [6,7,8] cannot be applied to circuits of which the exact structures are unknown [7].…”

Power-aware Test Generation for Reducing Yield Loss Risk in At-Speed Scan Testing

“…Previous techniques for reducing launch switching activity can be classified into two categories. Circuit-modification-based techniques include additional circuitry insertion [3,4], scan chain segmentation [5], scan re-ordering [6], and partial capturing [7], while data-manipulation-based techniques include test vector reordering [8], test generation [9,18], and X-filling [10][11][12][13][14]. Generally, the approach of data manipulation is preferable, since it avoids the cost of circuit overhead and the risk of performance degradation due to the approach of circuit modification.…”

“…Here, the goal is to reduce launch switching activity in at-speed scan testing. This is usually achieved by minimizing either the Hamming distance between a test vector and its response at FFs [10][11][12][13] or the weighted switching activity (WSA) for all nodes in a circuit [14].…”

“…The method in [13] is a typical hybrid technique employing two operations, namely limited justification and probability recalculation. The first operation is conducted for PPI-PPO bit-pairs of the form <logic value, X>, but not for any PPI-PPO bit-pair of the form <X, X> for which multiple passes of justification may be needed.…”