Small-delay faults may escape detection by transition fault patterns, but traditional transition fault simulator can not detect this phenomenon. A fault simulator detecting test escape of small-delay faults is presented. The sizes of the faults are less than one system clock cycle. For our method, the delay distribution in the CUT is considered, and the fault size is quantized as times of the propagation delay in an inverter. By a waveform simulation based on Boolean process, the simulator is able to show the time interval that the fault affects and determine whether the propagation delay exceeds the system clock cycle. It might give ATPG a little of useful information.

A memristor is regarded as a promising device for modeling synapses in the realization of artificial neural systems for its nanoscale size, analog storage properties, low energy and non-volatility. In this letter, an adaptive T-Model neural network based on CMOS/memristor hybrid design is proposed to perform the analog-to-digital conversion without oscillations. The circuit is composed of CMOS neurons and memristor synapses. The A/D converter (ADC) is trained by the least mean square (LMS) algorithm. The conductance of the memristors can be adjusted to convert input voltages with different ranges, which makes the ADC flexible. Using memristors as synapses in neuromorphic circuits can potentially offer high density.

Abstract:As an attractive option of future non-volatile memories (NVM), resistive random access memory (RRAM) has attracted more attentions. Due to its high density and low power, one memristor (1R) crossbar is a dominant RRAM structure. In this paper, we propose a logic operation-based design for testability (DFT) architecture for 1R crossbar testing. In this architecture, memristor-aided logic (MAGIC) NOR gates are embedded to check whether all the cells in the crossbar are 0 s or not at a time. A March-like test algorithm is also presented for the proposed architecture, which covers all modeled faults. The test time is reduced drastically with a little area overhead.

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As an attractive option of future non-volatile memories, resistive RAM (RRAM) has attracted more attentions. Among RRAM architectures, one transistor one memristor (1T1R) crossbar is the most fledged one. A March C*-1T1R algorithm is proposed for 1T1R crossbar. The pass-fail fault dictionary of the proposed March test algorithm is analysed. Analytical results show that the proposed test algorithm can detect all the modelled faults caused by the parametric variation of memristors, transistors and their interconnecting wires with a little test time overhead compared with previous methods. Stuck-at 1 (SA1): These faults can be sensitised by w0 and detected by r0. The faults are sensitised by M1, M3 or M5 and detected by M2, M4 or M6. SA0: These faults can be sensitised by w1 and detected by r1. The faults are sensitised by M2 or M4 and detected by M3 or M5. Deep-0: These faults can be initialised by two w0, be sensitised by w1 and detected by r1. Since the memristor of 1T1R crossbar undergoes a forming process, all memristors are initiated into LRS. The values of all 1T1R cells are logic 0 s. After forming operation, that is the first w0, M1 initialises the faults in the crossbar as the second w0. M2 sensitises the faults. Then, the faults can be detected by M3. Deep-1: These faults can be initialised by two w1, be sensitised by w0 and detected by r0. M4 initialises the faults as the first w1. M5 initialises the faults as the second w1. M5 also sensitises the faults. Then, the faults can be detected by M6. Deep-1/0: These faults have the characteristics of both Deep-1 and Deep-0 faults. Therefore, the test method of either Deep-1 or Deep-0 is also effective in detecting these faults. Slow Write 0 (SW0): These faults can be initialised by w1, sensitised by w0, and detected by r0. M2 or M5 initialises the faults. M3 or M5 sensitises the faults. Then, the faults can be detected by M4 or M6. SW1: These faults can be initialised by w0, sensitised by w1, and detected by r1. M1 or M3 initialises the faults. M2 or M4 sensitises the faults. Then, the faults can be detected by M3 or M5. R1D: During a read operation, if the data of a cell is flipped from logic 1 to logic 0, the cell has an R1D fault [8]. For these faults, there can be sensitised by r1 and detected by another succession of r1. In our March test algorithm, M3 sensitises and detects the faults. State CF (CFst): The CFst is defined that a victim cell is forced to a certain value only if the aggressor cell is in a given state. Therefore, there are four kinds of CFsts: CFst(0;0), CFst(0;1), CFst(1;0) and CFst(1;1). The first parameter in the parentheses represents for the operation of aggressor cell and the second parameter represents for the state of victim. In our March test algorithm, w1 in M2 initialises CFst(0;0). w0 in M3 sensitises CFst(0;0). r1 in M3 detects the CFst(0;0) in the victim cell which has lower address than the aggressor cell, named as CFst(0;0)>. In the similar way, CFst(0;0)<, CFst(1;1)< and CFst(1;1)>