A MEMS-Based Compliant Interconnect for Ultra-Fine-Pitch Wafer Level Packaging

Liao, E.B.; Tay, A.A.O.; Ang, Simon S.; Feng, Han; Nagarajan, Rajamani; Kripesh, V.; Kumar, R.; Iyer, M.K.

doi:10.1109/ectc.2006.1645812

Cited by 3 publications

(1 citation statement)

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“…Meander beams such as SoL and ELASTac may still have limited compliances because of the restraining effect of polymer underneath. To address or bypass these issues, a novel compliant chip-to-package interconnect scheme called planar microspring has been introduced earlier [25], and more details will be presented in this paper. As shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Planar Microspring—A Novel Compliant Chip-to-Package Interconnect for Wafer-Level Packaging

Liao

Tay

Ang

et al. 2009

IEEE Trans. Adv. Packag.

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In this paper, a novel compliant chip-to-package interconnect, planar microspring, is presented in terms of design consideration, wafer-level fabrication process and mechanical characterization. Several spring designs have been evaluated, and results indicate that a -shaped spring design produces a combination of high 3-D compliances and acceptable electrical parasitics. Further, numerical analyses on the -shaped microspring interconnect examined the dependence of mechanical and electrical performance upon geometry parameters. A wafer-level fabrication flow combining complementary metal oxide semiconductor (CMOS) back-end-of-line (BEOL) process and 3-D surface micromachining technique has been successfully implemented to create planar microspring interconnect prototypes with a fine pitch (100 m). The mechanical robustness of the prototype interconnects have been evaluated by nanoindentation. Finally, high-frequency electrical simulation suggested that the interconnect application can be extended up to 35 GHz without significant power loss.

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Section: Introductionmentioning

confidence: 99%