A Method Cache for Patmos

Degasperi, Philipp; Hepp, Stefan; Puffitsch, Wolfgang; Schoeberl, Martin

doi:10.1109/isorc.2014.47

Cited by 26 publications

(15 citation statements)

References 15 publications

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“…In contrast, the T-CREST processor Patmos uses a RISC instruction set to enable the execution of more traditional languages like C. A key feature of JOP is its cache architecture, with an instruction cache that caches whole methods [24] and separate caches for stack and heap data. Patmos keeps this general cache 175 architecture, but adapts it to fit a RISC instruction set [2,3]. Within the T-CREST project, we also adapted the analysis methodology developed for the object cache of JOP [25] in the analysis tool platin [26,27].…”

Section: Time-predictable Processorsmentioning

confidence: 99%

T-CREST: Time-predictable multi-core architecture for embedded systems

Schoeberl

Abbaspour

Åkesson

et al. 2015

Journal of Systems Architecture

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Real-time systems need time-predictable platforms to allow static analysis of the worst-case execution time (WCET). Standard multi-core processors are optimized for the average case and are hardly analyzable. Within the T-CREST project we propose novel solutions for time-predictable multi-core architectures that are optimized for the WCET instead of the average-case execution time. The resulting time-predictable resources (processors, interconnect, memory arbiter, and memory controller) and tools (compiler, WCET analysis) are designed to ease WCET analysis and to optimize WCET performance. Compared to other processors the WCET performance is outstanding.The T-CREST platform is evaluated with two industrial use cases. An application from the avionic domain demonstrates that tasks executing on different cores do not interfere with respect to their WCET. A signal processing application from the railway domain shows that the WCET can be reduced for computation-intensive tasks when distributing the tasks on several cores and using the network-on-chip for communication. With three cores the WCET is improved by a factor of 1.8 and with 15 cores by a factor of 5.7.The T-CREST project is the result of a collaborative research and development project executed by eight partners from academia and industry. The European Commission funded T-CREST.

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Section: Time-predictable Processorsmentioning

confidence: 99%

T-CREST: Time-predictable multi-core architecture for embedded systems

Schoeberl

Abbaspour

Åkesson

et al. 2015

Journal of Systems Architecture

Self Cite

170

100

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“…A main focus on Patmos is the memory hierarchy and the organization of local memories. For code Patmos contains a so-called method cache [6] and an instruction scratch-pad memory (ISPM). The method cache caches whole methods/functions to simplify WCET analysis.…”

Section: Patmosmentioning

confidence: 99%

Support for the logical execution time model on a time-predictable multicore processor

2016

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The logical execution time (LET) model increases the compositionality of real-time task sets. Removal or addition of tasks does not influence the communication behavior of other tasks. In this work, we extend a multicore operating system running on a timepredictable multicore processor to support the LET model. For communication between tasks we use message passing on a timepredictable network-on-chip to avoid the bottleneck of shared memory. We report our experiences and present results on the costs in terms of memory and execution time.

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“…The implementation of the M$ in Patmos [25] uses the organization with tag entries for individual methods and allocation granularity of single instruction words. However, this paper considers the original M$ organization in individual blocks as the SPM is also organized with block granularity.…”

Section: Definitionsmentioning

confidence: 99%

“…This is necessary in order to prevent memory fragmentation. The M$ has been implemented as part of the JOP CPU [14], as part of the SHAP CPU [30], as part of Patmos [25], and independently by Metzlaff et al [31]. The M$ hardware is more complex than the SPM hardware, as the search functionality is usually implemented in hardware.…”

Section: Execution Model For the M$mentioning

confidence: 99%

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WCET-Based Comparison of an Instruction Scratchpad and a Method Cache

Whitham

Schoeberl

2014

2014 IEEE 17th International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing

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Abstract-This paper compares two proposed alternatives to conventional instruction caches: a scratchpad memory (SPM) and a method cache. The comparison considers the true worstcase execution time (WCET) and the estimated WCET bound of programs using either an SPM or a method cache, using large numbers of randomly generated programs. For these programs, we find that a method cache is preferable to an SPM if the true WCET is used, because it leads to execution times that are no greater than those for SPM, and are often lower. However, we also find that analytical pessimism is a significant problem for a method cache. If WCET bounds are derived by analysis, the WCET bounds for an instruction SPM are often lower than the bounds for a method cache. This means that an SPM may be preferable in practical systems.

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A Method Cache for Patmos

Cited by 26 publications

References 15 publications

T-CREST: Time-predictable multi-core architecture for embedded systems

T-CREST: Time-predictable multi-core architecture for embedded systems

Support for the logical execution time model on a time-predictable multicore processor

WCET-Based Comparison of an Instruction Scratchpad and a Method Cache

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