A method for predicting the expected life of bus capacitors

Gasperi, Michael

doi:10.1109/ias.1997.628989

Cited by 60 publications

(49 citation statements)

References 4 publications

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“…The electrolytic capacitor model used in this analysis was introduced in [2] where it was shown to match well with experimental results, including lifetime prediction. The circuit diagram of the model is shown in Fig.…”

Section: Esr Model For Electrolytic Capacitormentioning

confidence: 86%

“…A curve fit to the model, done in MATLAB, is also shown in the figure. More series parallel RC segments can be added to produce a better fit [2], but a single pair results in sufficient accuracy to judge the relative change in losses. The resulting parameter values are shown in Table I.…”

Section: Esrmentioning

confidence: 99%

“…The experimental setup uses a TI TMS320F240 DSP to produce the gate signals with an identical modulation method. The modulation index used in the calculations is defined by (2) where is the fundamental output voltage and is the inverter modulation index [8]. Defined this way the ideal limit of the linear modulation region for SVPWM is when .…”

Section: Determination Of Capacitor Current Spectrum Of Vsi Drivementioning

confidence: 99%

“…The focus of this paper is the inverter contribution, since with proper design the rectifier contribution to the ripple current can be made negligible (i.e., by adding a large enough ac-or dc-side reactor) [1], [2]. Operating temperature is the main factor causing degradation of the capacitor parameters, especially the ESR.…”

Section: Introductionmentioning

confidence: 99%

“…At some point the ESR will exceed the maximum recommended value (termed parameter drift failure [3]). This is considered the end of life for the capacitor at which time it should be replaced [2].…”

Section: Introductionmentioning

confidence: 99%

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Reduction of DC-Bus Capacitor Ripple Current With PAM/PWM Converter

Kieferndorf

Forster

Lipo

2004

IEEE Trans. on Ind. Applicat.

119

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Abstract-Electrolytic capacitors are used in nearly all adjustable-speed drives, and they are one of the components most prone to failure. The main failure mechanisms include loss of electrolyte through outgassing and chemical changes to the electrolyte and oxide layer. All the degradation mechanisms are exacerbated by ripple current heating. Since the equivalent series resistance of electrolytic capacitors is a very strong function of frequency it must be properly modeled to accurately calculate the power loss. In this paper, a method to reduce the ripple current in a constant Volts/Hertz pulse-amplitude-modulation (PAM)/pulsewidth-modulation (PWM) converter driving an induction motor is investigated. The dc-bus voltage amplitude is reduced in proportion to speed by a buck or current stiff rectifier and the PWM modulation index is maintained at a high level to achieve a reduced ripple current below base speed. By comparison with a diode-bridge-fed PWM voltage stiff inverter, it is shown that the PAM/PWM mode of operation can lead to a significant reduction in capacitor power loss leading to increased capacitor lifetime or decreased capacitor size. The capacitor heating is analyzed using numerical and analytical techniques. Experimental results are provided to verify the analytical results.Index Terms-Adjustable-speed drive (ASD), buck rectifier, current ripple, current stiff rectifiers (CSRs), electrolytic capacitor modeling, equivalent series resistance (ESR), industrial drives, pulse amplitude modulation (PAM), pulsewidth modulation (PWM), voltage stiff inverter (VSI).

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Section: Esr Model For Electrolytic Capacitormentioning

confidence: 86%

Section: Esrmentioning

confidence: 99%

Section: Determination Of Capacitor Current Spectrum Of Vsi Drivementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Reduction of DC-Bus Capacitor Ripple Current With PAM/PWM Converter

Kieferndorf

Forster

Lipo

2004

IEEE Trans. on Ind. Applicat.

119

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Harmonic analysis of DC capacitor current in sinusoidal and space-vector modulated neutral-point-clamped inverters

Gopalakrishnan

Narayanan

2015

Sadhana

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The voltage ripple and power loss in the DC-capacitor of a voltage source inverter depend on the harmonic currents flowing through the capacitor. This paper presents a double Fourier series based analysis of the harmonic contents of the DC capacitor current in a three-level neutral-point clamped (NPC) inverter, modulated with sine-triangle pulse-width modulation (SPWM) or conventional space vector pulse-width modulation (CSVPWM) schemes. The analytical results are validated experimentally on a 3-kVA three-level inverter prototype. The capacitor current in an NPC inverter has a periodicity of 120 • at the fundamental or modulation frequency. Hence, this current contains third-harmonic and triplen-frequency components, apart from switching frequency components. The harmonic components vary with modulation index and power factor for both PWM schemes. The third harmonic current decreases with increase in modulation index and also decreases with increase in power factor in case of both PWM methods. In general, the third harmonic content is higher with SPWM than with CSVPWM at a given operating condition. Also, power loss and voltage ripple in the DC capacitor are estimated for both the schemes using the current harmonic spectrum and equivalent series resistance (ESR) of the capacitor.

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