A method for testability analysis and BIST insertion at the RTL

Abstract

The goal of this research is to provide a means for BIST and circular BIST analysis and evaluation at the register transfer level (RTL). RTL circuits consist of interconnections of registers, functional units (ALUs), multiplexers and buses. The analysis is done via two metrics that measure the eectiveness with which a n individual register in the circuit generates test patterns, the entropy-based randomness [1] and expected state coverage.The testability metrics are computed by means of a Markov c hain model that takes as input the RTL circuit description, and provides analytical values for the probability distribution of the state of each register in the circuit. The Markov model works by partitioning the circuit into small pieces, each containing the information necessary to analyze a single register. It then models each register separately as the register moves from state to state. A wide variety of BIST methodologies, including conventional, MISR-based, and circular BIST, can be modeled with this technique.The motivation for this work lies in BIST insertion, which requires the selection of test registers. Traditionally, each ALU in a circuit is made directly testable by placing controllable registers (TPGRs) at the ALU's inputs, and observable registers (MISRs) at the ALU's output. However, this addition of test registers may not be necessary. F or example, suppose that the input registers to the ALU are not directly controllable, but that they still generate patterns that are random enough to eectively test the ALU; in this case, there is no need to replace the registers with more expensive test pattern generation registers. Thus, in selecting test registers, a tradeo between cost and test eectiveness can be made; using fewer test registers will save hardware and have a less negative impact on system performance, but may h a v e a n a d v erse ef- fect on test quality. The testability metrics are used to evaluate various BIST congurations for a given RTL structure, and thus they provide a mechanism for the cost / test eectiveness tradeo.The Markov model used here is more general than the previous models [2,3] in three main ways. First, a preprocessing transformation is used to remove reconvergent fanout from RTL circuits, allowing the eects of word-level correlation on test quality to be accurately modeled. The transformation technique serves to subsume the reconvergent fanout within the combinational logic, where it can be taken into account easily. Second, an iterative technique is developed so that the model can handle circuits with indirect feedback, i.e., circuits in which a register feeds back i n to itself via one or more intermediate registers. Finally, the model is extended to include the circular BIST methodology.The proposed Markov model has been used to analyze several example circuits. These examples serve two purposes: to validate the model by showing that the analytical predictions are close to actual results obtained by simulation, and to show how the metrics can be used to guide tes...