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The goal of this research is to provide a means for BIST and circular BIST analysis and evaluation at the register transfer level (RTL). RTL circuits consist of interconnections of registers, functional units (ALUs), multiplexers and buses. The analysis is done via two metrics that measure the eectiveness with which a n individual register in the circuit generates test patterns, the entropy-based randomness [1] and expected state coverage.The testability metrics are computed by means of a Markov c hain model that takes as input the RTL circuit description, and provides analytical values for the probability distribution of the state of each register in the circuit. The Markov model works by partitioning the circuit into small pieces, each containing the information necessary to analyze a single register. It then models each register separately as the register moves from state to state. A wide variety of BIST methodologies, including conventional, MISR-based, and circular BIST, can be modeled with this technique.The motivation for this work lies in BIST insertion, which requires the selection of test registers. Traditionally, each ALU in a circuit is made directly testable by placing controllable registers (TPGRs) at the ALU's inputs, and observable registers (MISRs) at the ALU's output. However, this addition of test registers may not be necessary. F or example, suppose that the input registers to the ALU are not directly controllable, but that they still generate patterns that are random enough to eectively test the ALU; in this case, there is no need to replace the registers with more expensive test pattern generation registers. Thus, in selecting test registers, a tradeo between cost and test eectiveness can be made; using fewer test registers will save hardware and have a less negative impact on system performance, but may h a v e a n a d v erse ef- fect on test quality. The testability metrics are used to evaluate various BIST congurations for a given RTL structure, and thus they provide a mechanism for the cost / test eectiveness tradeo.The Markov model used here is more general than the previous models [2,3] in three main ways. First, a preprocessing transformation is used to remove reconvergent fanout from RTL circuits, allowing the eects of word-level correlation on test quality to be accurately modeled. The transformation technique serves to subsume the reconvergent fanout within the combinational logic, where it can be taken into account easily. Second, an iterative technique is developed so that the model can handle circuits with indirect feedback, i.e., circuits in which a register feeds back i n to itself via one or more intermediate registers. Finally, the model is extended to include the circular BIST methodology.The proposed Markov model has been used to analyze several example circuits. These examples serve two purposes: to validate the model by showing that the analytical predictions are close to actual results obtained by simulation, and to show how the metrics can be used to guide tes...

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In systems consisting of interacting datapaths and controllers, the datapaths and controllers are traditionally tested separately by isolating each component from the environment of the system during test. This is not possible when the controller-datapath pair is an embedded system designed as a hard core. This work facilitates the testing of controller-datapath pairs in a truly integrated fashion.The key to the approach is a careful examination of the types of gate level stuck-at faults that can occur within the controller. A class of faults that are undetectable in an integrated test by traditional means is identified. These faults create faulty but functional circuits. The effect of these faults on power consumption is explored, and a method based on power analysis is given for detecting these faults. Analysis is given for three example systems. ½ ÁÒØÖÓ Ù Ø ÓÒThis work addresses the problem of testing systems that consist of interacting datapaths and controllers, and facilitates the testing of these controller-datapath pairs in an integrated fashion. Typically, testing of datapaths and controllers is done independently, rather than as two parts of an inseparable pair. However, the separation may not be feasible in embedded system designs where the controller-datapath is a reusable component or core to be integrated in a system-on-chip. Separate testing does not adequately cover the interface between the controller and the datapath.Few, if any, design tools address the issue of how to test datapath and controller in an integrated way. The main difficulty in integrated testing is the need to propagate controller faults through the datapath for observation at the datapath outputs. In their work on integrating controller and datapath test, Dey et. al. observed that even when the controller and datapath are 100% testable separately, the combination of them has usually much lower coverage. This degradation, in their opinion, occurs due to the correlation and dependency between the control signals[8].In our recent work [16] we addressed the problem of integrated test, and provided a test synthesis method to allow the controller to be easily tested as part of the integrated system. However, our method required design-for-testability insertion at the controllerdatapath interface, and therefore is not appropriate for embedded cores. In our work we came across a new type of system-level redundant fault, originating in the controller, that while having no functional effect yet produces an undesirable power increase during normal system operation. This issue has been the motivation and focus of our present work. The key to our approach is a careful analysis of the system-functionally redundant faults, which are undetectable in any traditional test that treats the pair as an integrated system. What we found is that many of these faults have a significant, measurable effect on dynamic power consumption. We remark here that these faults can not be caught by IDDQ techniques [1], which measure quiescent current. TX 75083.To the...