A method of leakage reduction and slew-rate adjustment in 2×VDD output buffer for 28 nm CMOS technology and above

Tsai, Tsung-Heng; Chou, Yan-You; Wang, Chua-Chin

doi:10.1109/icicdt.2016.7542043

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A method of leakage reduction and slew-rate adjustment in 2×VDD output buffer for 28 nm CMOS technology and above

Cited by 5 publications

References 15 publications

A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process

A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process

A Sigma-Delta ADC with Complementary T-Switch

2.5 GHz Data Rate 2 × VDD Digital Output Buffer Design Realized by 16-nm FinFET CMOS

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