A Methodology for Rapid Prototyping Peak-Constrained Least-Squares Bit-Serial Finite Impulse Response Filters in FPGAs

Abstract

Area-efficient peak-constrained least-squares (PCLS) bit-serial finite impulse response (FIR) filter implementations can be rapidly prototyped in field programmable gate arrays (FPGA) with the methodology presented in this paper. Faster generation of the FPGA configuration bitstream is possible with a new application-specific mapping and placement method that uses JBits to avoid conventional general-purpose mapping and placement tools. JBits is a set of Java classes that provide an interface into the Xilinx Virtex FPGA configuration bitstream, allowing the user to generate new configuration bitstreams. PCLS coefficient generation allows passband-to-stopband energy ratio (PSR) performance to be traded for a reduction in the filter's hardware cost without altering the minimum stopband attenuation. Fixed-point coefficients that meet the frequency response and hardware cost specifications can be generated with the PCLS method. It is not possible to meet these specifications solely by the quantization of floating-point coefficients generated in other methods

A new local search method to design finite precision FIR filters

“…Very little research has been presented on designing PCLS FIR filters with low complexity finite precision coefficients, which requires controlling simultaneously the coefficient complexity ( Lagrangian local search methods [5][6][7] , which are based on the condition that the set of discrete saddle points is the same as the set of discrete constrained local minima when all constraint functions are non-negative [8] , have been applied in rapid prototyping [9] and low cost design [10] of the PCLS FIR filters.…”