A Methodology to Derive a Symbolic Transfer Function for Multistage Amplifiers

Aminzadeh, Hamed; Grasso, Alfio Dario; Palumbo, G.

doi:10.1109/access.2022.3147879

Cited by 12 publications

(10 citation statements)

References 65 publications

(79 reference statements)

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“…The main elements of the frequency compensation network are the series R D1 , C D1 , and R D2 , C D2 around the second and the third stages, respectively, besides the Miller C C /2 capacitors between v O and the source of M 6 and M 8 that implement the embedded g mC transconductances without any power overhead. These devices with a relatively light 1/g mC input impedance close the parallel feedback pathways from v O to the input, moving a right-half-plane (RHP) zero to very high frequencies by minimizing a feedforward current to flow to the output via either C C /2 [34]. The hybrid nature of the compensation network also allows designers to achieve a balanced time response during the falls and rises of v O , unlike the classical solution which possibly connects C C to the source of M 6 or M 8 .…”

Section: Proposed Topologymentioning

confidence: 99%

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Hybrid Cascode Frequency Compensation for Four-Stage OTAs Driving a Wide Range of C _L

Aminzadeh,

Ballo,

Grasso

et al. 2023

IEEE Trans. VLSI Syst.

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Feedback amplifiers consisting of multiple gain stages are used to establish highly accurate buffered/amplified signals that can drive a wide range of capacitive load (CL). This article models, analyzes, and presents the measurement results of a high-gain four-stage operational transconductance amplifier (OTA) that is able to handle a wide range of CL up to infinity. In addition to local compensation capacitors and nulling resistors in the intermediate stages, two high-speed feedback loops made by parallel Miller capacitors and current buffers provide Miller compensation and the consequent pole-splitting in the lower CL range. The dominant pole is made dependent on the CL for the higher CL range, enabling the maintenance of the stability conditions up to infinite CL. The proposed amplifier was integrated into a 65-nm CMOS technology, consuming 140-µA static current under a 1.2-V supply and an active area of 0.0086 mm 2 . A dc gain greater than 100 dB was also perceived with a unity-gain frequency (UGF) of 4.09, 2.01, and 0.27 MHz for 4.7, 10, and 100-nF load capacitors, respectively. The average slew rate (SR) is 0.59 V/µs, when the OTA is formed as a buffer targeting the CLs higher than 4.7-nF.

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Section: Proposed Topologymentioning

confidence: 99%

“…for the output impedances are subsequently dominated by C L , g mi and compensation elements. Under these circumstances, the methodology described in [34] can be used to approximate v O /v i as…”

Section: B Small-signal Analysismentioning

confidence: 99%

Hybrid Cascode Frequency Compensation for Four-Stage OTAs Driving a Wide Range of C _L

Aminzadeh,

Ballo,

Grasso

et al. 2023

IEEE Trans. VLSI Syst.

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“…1. the equivalent transconductance of all stages is much greater than their output conductance (g mi , g m2 , g mL 1/R i ); 2. the nulling resistor R C is much lower than R D and both are much smaller than the output resistors (R C R D R i ); 3. the compensation capacitors are much lower than the load capacitor and all are much larger than the parasitic capacitors (C L C C , C D C i ), the simplified amplifier transfer function, using the methodology described in [43], can be expressed by…”

Section: B Transfer Functionmentioning

confidence: 99%

Frequency Compensation of Three-Stage OTAs to Achieve Very Wide Capacitive Load Range

2022

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This paper proposes an optimal design approach for three-stage amplifiers driving an ultra-wide range of load capacitor. To this end, efficient state-of-the-art solutions have been combined to develop a power-efficient frequency compensation solution. High-speed feedback pathways relying on Miller capacitors and current buffers are implemented within the amplifier scheme to push the non-dominant poles to high frequencies for small to medium load capacitors. A small resistor is also shared between the two pathways to improve the stability regardless of the load capacitor. A serial R-C branch is then added to extend the lower limit of load drive capability to small load capacitors. Gain margin is, for the first time in literature, analytically evaluated and included in the design phase. A prototype of the proposed amplifier is fabricated in 65-nm CMOS process with active area of 0.0017 mm 2 and 1.15 pF total compensation capacitance. It can drive the load capacitor range from 200 pF to 100 nF, while drawing a quiescent current of 7.4 µA from a 1.2-V input voltage supply. A unity-gain frequency of 1.67 MHz was measured with an average slew-rate of 1.31 V/µs, when the proposed amplifier is wired in unity-gain configuration to drive a 500-pF load capacitor.

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“…Generally, an exact symbolic analysis of OTAs is error-prone and time-consuming if it is done by hand, even for circuits with a small number of components [6]. In this regard, a computer-aided automatic symbolic resolution can be helpful by solving the circuit equations by mathematical solvers such as Cramer's rule [7].…”

Section: Introductionmentioning

confidence: 99%

Mathematical Root Simplification in Operational Amplifiers using an Ensemble Heuristic-Metaheuristic Algorithm

Behmanesh-Fard¹,

Yazdanjouei²,

Shokouhifar³

et al. 2023

Preprint

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Symbolic pole/zero analysis is an important step when designing an analog operational amplifier. Generally, a simplified symbolic analysis of analog circuits suffers from NP-hardness, i.e., an exponential growth of the number of symbolic terms of the transfer function with the circuit size. In this study, we present a mathematical model combined with a heuristic-metaheuristic solution method for the symbolic pole/zero simplification in operational transconductance amplifiers (OTA). At first, the circuit is symbolically solved and an improved root splitting method is applied to extract symbolic poles/zeroes from the exact expanded transfer function. Then, a hybrid algorithm based on heuristic information and a metaheuristic technique using simulated annealing is performed for the simplification of the derived symbolic pole/zero expressions. The developed method has been tested on three analog OTAs. The obtained results show the effectiveness of the proposed method to achieve accurate simplified symbolic pole/zero expressions with the least complexity.

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A Methodology to Derive a Symbolic Transfer Function for Multistage Amplifiers

Cited by 12 publications

References 65 publications

Hybrid Cascode Frequency Compensation for Four-Stage OTAs Driving a Wide Range of C _L

Hybrid Cascode Frequency Compensation for Four-Stage OTAs Driving a Wide Range of C _L

Frequency Compensation of Three-Stage OTAs to Achieve Very Wide Capacitive Load Range

Mathematical Root Simplification in Operational Amplifiers using an Ensemble Heuristic-Metaheuristic Algorithm

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A Methodology to Derive a Symbolic Transfer Function for Multistage Amplifiers

Cited by 12 publications

References 65 publications

Hybrid Cascode Frequency Compensation for Four-Stage OTAs Driving a Wide Range of C L

Hybrid Cascode Frequency Compensation for Four-Stage OTAs Driving a Wide Range of C L

Frequency Compensation of Three-Stage OTAs to Achieve Very Wide Capacitive Load Range

Mathematical Root Simplification in Operational Amplifiers using an Ensemble Heuristic-Metaheuristic Algorithm

Contact Info

Product

Resources

About

Hybrid Cascode Frequency Compensation for Four-Stage OTAs Driving a Wide Range of C _L

Hybrid Cascode Frequency Compensation for Four-Stage OTAs Driving a Wide Range of C _L