A microprocessor with a 128 b CPU, 10 floating-point MACs, 4 floating-point dividers, and an MPEG2 decoder

Kutaragi, K.; Suzuoki, M.; Hiroi, T.; Magoshi, H.; Okamoto, S.; Oka, Masaaki; Ohba, A.; Yamamoto, Y.; Furuhashi, M.; Tanaka, M.; Tanaka, Yutaka; Okada, Tomoyuki; Nagamatsu, M.; Urakawa, Y.; Funyu, M.; Kunimatsu, Atsushi; Goto, H.; Hashimoto, K.; Ide, N.; Murakami, Hiroaki; Ohtaguro, Y.; Aono, A.

doi:10.1109/isscc.1999.759229

Cited by 8 publications

(5 citation statements)

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“…The first objective of Cell was to achieve a substantial improvement over the state of the art in performance per watt while still maintaining programmability. Sony and Toshiba had experience with the Emotion Engine ** [1] processor with an accelerator processor whose memory could be accessed only via DMA. Since a large fraction of the power and chip area on conventional processors is associated with caches, it appeared that this model could provide for a more efficient computational element.…”

Section: How the Concept Addresses The Design Objectivesmentioning

confidence: 99%

Introduction to the Cell multiprocessor

Kahle¹,

Day²,

Hofstee³

et al. 2005

IBM J. Res. & Dev.

704

442

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This paper provides an introductory overview of the Cell multiprocessor. Cell represents a revolutionary extension of conventional microprocessor architecture and organization. The paper discusses the history of the project, the program objectives and challenges, the design concept, the architecture and programming models, and the implementation. Introduction: History of the project Initial discussion on the collaborative effort to develop Cell began with support from CEOs from the Sony and IBM companies: Sony as a content provider and IBM as a leading-edge technology and server company. Collaboration was initiated among SCEI (Sony Computer Entertainment Incorporated), IBM, for microprocessor development, and Toshiba, as a development and high-volume manufacturing technology partner. This led to high-level architectural discussions among the three companies during the summer of 2000. During a critical meeting in Tokyo, it was determined that traditional architectural organizations would not deliver the computational power that SCEI sought for their future interactive needs. SCEI brought to the discussions a vision to achieve 1,000 times the performance of PlayStation2** [1, 2]. The Cell objectives were to achieve 100 times the PlayStation2 performance and lead the way for the future. At this stage of the interaction, the IBM Research Division became involved for the purpose of exploring new organizational approaches to the design. IBM process technology was also involved, contributing state-of-the-art 90-nm process with silicon-on-insulator (SOI), low-k dielectrics, and copper interconnects [3]. The new organization would make possible a digital entertainment center that would bring together aspects from broadband interconnect, entertainment systems, and supercomputer structures. During this interaction, a wide variety of multi-core proposals were discussed, ranging from conventional chip multiprocessors (CMPs) to dataflow-oriented multiprocessors. By the end of 2000 an architectural concept had been agreed on that combined the 64-bit Power Architecture* [4] with memory flow control and ''synergistic'' processors in order to provide the required computational density and power efficiency. After several months of architectural discussion and contract negotiations, the STI (SCEI-Toshiba-IBM) Design Center was formally opened in Austin, Texas, on March 9, 2001. The STI Design Center represented a joint investment in design of about $400,000,000. Separate joint collaborations were also set in place for process technology development. A number of key elements were employed to drive the success of the Cell multiprocessor design. First, a holistic design approach was used, encompassing processor architecture, hardware implementation, system structures, and software programming models. Second, the design center staffed key leadership positions from various IBM sites. Third, the design incorporated many flexible elements ranging from reprogrammable synergistic processors to reconfigurable I/O interfaces in order to suppor...

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Section: How the Concept Addresses The Design Objectivesmentioning

confidence: 99%

Introduction to the Cell multiprocessor

Kahle¹,

Day²,

Hofstee³

et al. 2005

IBM J. Res. & Dev.

704

442

View full text Add to dashboard Cite

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“…The details were reported at ISSCC1999 [1][2] and at HOTCHIPS1999 [3]. It was the world's first 128-bit microprocessor with two sets of coprocessors based on floating-point functionality for graphics and animation.…”

Section: Emotion Enginementioning

confidence: 99%

Toward Future Computer Entertainment Systems

Kutaragi¹

2006

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

Self Cite

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I. THE BIRTH OF COMPUTERSSixty years have passed since the birth of ENIAC, utilizing over 18,800 vacuum tubes; 35 years have passed from the birth of the world's first microprocessor the "4004", integrating more than 2300 transistors. During these years, dramatic advances have been made in semiconductor process technology. Today, the most advanced microprocessor integrates several hundreds of millions of transistors on a single silicon chip, and boasts computing power a million times greater than that of the first microprocessor. Also, thanks to advances in semiconductor process technology, downsizing of chips has progressed, making it possible for PCs to excel in various applications, and significant improvements have been made in computing. II. REAL-TIME COMPUTINGThe main thrust of general-purpose computers is to process various and broad office applications, precisely and efficiently. Realtime responsiveness is generally not important. As well, software systems for general-purpose computers became more and more complicated, "comfortable" operation that was natural in analog and mechanical systems has been gradually lost. Even with a PC that incorporates the latest microprocessor and memory system, users are frustrated by the computer system stalling when accessing large files such as encountered in moving images, and even worse, the system itself sometimes freezes. One of the reasons for such performance degeneration is that both microprocessors and operating systems have made continuous efforts to downsize existing systems, while coping with the inherited architectures of traditional main-frame computers. Today, a wide range of applications can be realized by software solutions on general-purpose computers instead of by dedicated hardware; thus many hardware solutions are being taken over by computer systems. This is a rational progression, brought about by technology. Nevertheless, as a result of operation becoming more complicated, and real-time responsiveness largely disappearing, instinctive and intuitive behaviours expected by human beings become more and more absent. The user is compelled to read through hundreds of pages of manuals to uncover procedures and protocols, or to attend special computer schools. However, such knowledge, however obtained, soon becomes outdated. This is one of the causes for human hesitation in adopting computers.On the other hand, when real-time responsiveness is emphasized, there are two elements that a human being can intuitively sense; One is the seamless continuity of motion that a human being cognitively feels to be real; and the other is the discernable predictability of the response time between action and reaction. Thus, currently, the frame rate required to allow consecutive still images to be perceived as a moving image is 24 frames per second, in the case of film, and 50 to 60 frames per second, in the case of NTSC/PAL TV systems. In the future, frame rate will be enhanced to become even higher for improving the fidelity of "expression". Researchers report that hum...

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“…Automated clock tree tuning is also an indispensable technique to build up a large scale microprocessor in a limited design period. This paper will discuss the clock distribution methodology and the clock tree tuning flow for a 300MHz 128-bit 2-way superscalar microprocessor [6], [7]. Both of the techniques enable us to reduce the simulated clock skew to less than 116ps.…”

Section: Inmentioning

confidence: 99%

Clock design of 300MHz 128-bit 2-way superscalar microprocessor

Ishihara

Klinger

Agawa

2000

Proceedings of the 2000 Conference on Asia South Pacific Design Automation - ASP-DAC '00

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Less than 116ps overall clock skew has been achieved across the 15.02mm 15.04mm die by balanced clock path routing and differential clock signal distribution in the global clock tree of 300MHz 128-bit 2-way superscalar microprocessor. The shared clock wire configuration and clock buffer layout patterns over the whole die enhance the clock skew insensitivity to process fluctuation. Combination of three different clock tuning methods is successfully applied to the entire clock tree and the clock skew is minimized efficiently within a limited design period.

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A microprocessor with a 128 b CPU, 10 floating-point MACs, 4 floating-point dividers, and an MPEG2 decoder

Cited by 8 publications

References 0 publications

Introduction to the Cell multiprocessor

Introduction to the Cell multiprocessor

Toward Future Computer Entertainment Systems

Clock design of 300MHz 128-bit 2-way superscalar microprocessor

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