A million wafer, virtual fabrication approach to determine process capability requirements for an industry-standard 5nm BEOL two-level metal flow

Clark, William F.; Juncker, A.; Paladugu, E.; Fried, D.; Wilson, Christopher J.; Pourtois, Geoffrey; Gallagher, Michael; Jamblinne, A. De; Piumi, Daniele; Boemmels, J.; Tőkei, Zsolt; Mocuta, Dorina-Nicoleta

doi:10.1109/sispad.2016.7605144

Cited by 3 publications

(2 citation statements)

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“…However, both approaches lack the necessary speed and large area modeling capability that is needed for predictive process development at advanced nodes. The use of virtual process modeling and metrology is also applicable to disruptive technology changes such as material changes or process flow changes that require fast turnaround understanding of any potential impacts to the process flow due to the disruptive technology change 11 – 13 …”

Section: Introductionmentioning

confidence: 99%

“…The use of virtual process modeling and metrology is also applicable to disruptive technology changes such as material changes or process flow changes that require fast turnaround understanding of any potential impacts to the process flow due to the disruptive technology change. [11][12][13] In this paper, we demonstrate the ability of process modeling, 3D virtual wafer fabrication, and virtual metrology to gain insight into the most advanced technology logic and memory technologies. We start by examining a state-of-the-art 3D NAND structure 14 and its evolution from 96 tier stacks to 128 and beyond.…”

Section: Introductionmentioning

confidence: 99%

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Review of virtual wafer process modeling and metrology for advanced technology development

Hargrove

Wen

Yim

et al. 2023

J. Micro/Nanopattern. Mats. Metro.

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Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the process flow and ultimately quantifying its physical and electrical properties are critical steps in yielding mature technology. The standard build, test, and wait model of technology development is a major contributor to time and cost overruns. The growing inability to characterize many of the subtle and complicated features and yield limiting factors of a given technology is another serious constraint. We demonstrate the use of process modeling, virtual wafer fabrication, and virtual metrology in process development of advanced logic and memory. Accurate and predictive process modeling, in combination with virtual metrology enables the characterization of any feature on any given structure, is becoming a key requirement in advanced technology development. Virtual fabrication also accelerates the semiconductor development cycle, by substituting limited and lengthy wafer-based experiments with fast, large-scale virtual design of experiment. Several applications of virtual process modeling and metrology are illustrated in 3D NAND, DRAM, and logic technology. These applications include studies of 3D NAND pillar etch alignment (including tilt, twist, and bowing), DRAM capacitor process window optimization, advanced FinFET logic pitch-walking, and BEOL performance optimization.

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Section: Introductionmentioning

confidence: 99%