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For devices beyond the 14nm node, it is important to investigate performance boosters such as high mobility channels. Although pure Ge offers a higher hole mobility than Si, conventional problems like surface passivation and its integration with Si makes SiGe alloy with low Ge mole fraction a viable option. The significance of alloy scattering, however, has been widely debated [1-3], so the accurate modeling of alloy scattering in SiGe channel has become an important issue to predict the performance of future SiGebased FETs. Usually, the calculation of alloy scattering mobility assumes an alloy scattering center in a simple analytical form with some fitting parameters, which is a good practical approach but has a limited predictability. In this paper, an atomistic tight-binding simulation is used to study alloy scattering in SiGe-based FETs, and to compare with experimental data. We conclude (i) although it is essentially impossible to avoid alloy scattering in SiGe material, (ii) high-mobility is indeed achieved in SiGe channel by combining lattice-mismatch stresses from Si virtual substrate with stresses from Source/Drain(SD) stressor.

AbstractsHigh-k/metal gate (HKMG) compatible high performance Source/Drain (S/D) stress-memorization-technology (SMT) is presented. Channel stress generated by SMT can be simulated by using mask-edge dislocation model, which is consistent with the measured actual channel stress. Extremely deep pre-amorphization-implant (PAI) for SMT creates multiple mask-edge dislocations under S/D region, which enhances short-channel mobility by 40~60%. Finally, more than 10% short channel drive current gain is achieved with additional S/D extension optimization.

This paper reports the design and fabrication of a practical Si nanowire (NW) transistor for beyond 10 nm logic devices application. The dependency of the DC and AC performances of Si NW MOSFETs on NW diameter (D NW ) and gate oxide thickness has been investigated. A Si NW device with the scaled D NW of 9nm and thin equivalent oxide thickness (EOT) of 0.9nm improved both on-current and electrostatic characteristics. Finally, a Nanowire-On-Insulator (NOI) structure has been proposed to enhance the AC performance of a multiple-stacked NWs structure, which improves DC performance but has the issue of high parasitic capacitance. As a result, the simulated AC performance of a triple-NOI structure was improved by around 20% compared to conventional triple NW structure.