A practical Si nanowire technology with nanowire-on-insulator structure for beyond 10nm logic technologies

Hur, Sung-Gi; Yang, Jung-Gil; Kim, Sang-Su; Lee, Dong‐Kyu; An, Taehyun; Nam, Kab-Jin; Kim, Seong-Je; Wu, Zhenhua; Lee, Won-Sok; Kwon, Uihui; Lee, Keun-Ho; Park, Young-Kwan; Yang, Wonyoung; Choi, Jung Han; Kang, Ho-Kyu; Jung, Eun-Sung

doi:10.1109/iedm.2013.6724698

Cited by 26 publications

(5 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In particular, InAs nanowires have been shown to have a mobility at least an order of magnitude higher than that of silicon nanowires. 2,3 Moreover, the ease by which ohmic contacts are formed into In x Ga 1Àx As and the possibility of low-defect high-k oxide interfaces have made In x Ga 1Àx As one of the primary considerations as the replacement for silicon channels in n-type metal-oxide-semiconductor field-effect transistors (MOSFETs). 4À7 The implementation of IIIÀV MOSFETs, such as In x Ga 1Àx As, will likely be in the form of 1D nanowires with diameters less than 30 nm.…”

mentioning

confidence: 99%

“…Indium-rich In x Ga 1– x As nanowires have gathered much research attention recently due to their excellent electron transport properties . In particular, InAs nanowires have been shown to have a mobility at least an order of magnitude higher than that of silicon nanowires. , Moreover, the ease by which ohmic contacts are formed into In x Ga 1– x As and the possibility of low-defect high-k oxide interfaces have made In x Ga 1– x As one of the primary considerations as the replacement for silicon channels in n-type metal-oxide-semiconductor field-effect transistors (MOSFETs). − The implementation of III–V MOSFETs, such as In x Ga 1– x As, will likely be in the form of 1D nanowires with diameters less than 30 nm . The use of nanowires as the channel in MOSFETs offers enhanced performance compared to traditional planar channels, through improved electrostatic control.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Quantized Conduction and High Mobility in Selectively Grown In_xGa_1–xAs Nanowires

et al. 2015

View full text Add to dashboard Cite

We report measured quantized conductance and quasi-ballistic transport in selectively regrown In0.85Ga0.15As nanowires. Very low parasitic resistances obtained by regrowth techniques allow us to probe the near-intrinsic electrical properties, and we observe several quantized conductance steps at 10 K. We extract a mean free path of 180 ± 40 nm and an effective electron mobility of 3300 ± 300 cm(2)/V·s, both at room temperature, which are among the largest reported values for nanowires of similar dimensions. In addition, optical characterization of the nanowires by photoluminescence and Raman measurement is performed. We find an unintentional increase of indium in the InxGa1-xAs composition relative to the regrown film layer, as well as partial strain relaxation.

show abstract

mentioning

confidence: 99%

mentioning

confidence: 99%

Quantized Conduction and High Mobility in Selectively Grown In_xGa_1–xAs Nanowires

et al. 2015

View full text Add to dashboard Cite

show abstract

“…Hence our approach presents a unique technique for fabricating very thin, monocrystalline Si nanowires with circular cross sections. This meets the key fabrication requirement for functional electron channels in the next-generation vertical GAAFETs. − …”

Section: Resultsmentioning

confidence: 79%

Controlling the Wet-Etch Directionality in Nanostructured Silicon

Aabdin

Ghosh

Pacco

et al. 2022

ACS Appl. Electron. Mater.

View full text Add to dashboard Cite

Anisotropic wet etching of crystalline silicon (c-Si) is a key chemical process used in microelectronic device fabrication. Controlled fabrication of c-Si nanostructures requires an understanding of how crystal planes evolve during silicon etching. Here, by imaging KOH wet etching of c-Si nanowires, we show that it is possible to switch the fast-etching direction (i.e., the etch anisotropy) between the Si {100} and {110} crystal planes at will through mechanical agitation of the etchant. Based on molecular dynamics simulations, we attribute this switching to the higher affinity of the Si(OH)4 etch byproducts to the Si {110} planes. These surface-bound byproducts hinder etchant access to the {110} surfaces under stationary etching conditions and thus reduce the etch rate in ⟨110⟩ directions. Most importantly, by cycling through stirred and stationary modes of etching, we can obtain isotropic etch profiles, fabricating high-quality, round Si nanowires with sub-10 nm diameters. Our study provides an important insight into the nanoscale wet etching of Si and demonstrates a new level of control for enabling highly scalable, advanced nanoelectronic devices.

show abstract

“…e transistor features high-k/metal gate stacks. It exhibits very good shortchannel characteristics: subthreshold slope SS ≈ 74 mV/dec, DIBL ≈ 50 mV/V [46].…”

Section: Nanowire and Nanosheet Transistorsmentioning

confidence: 99%

Technology and Modeling of Nonclassical Transistor Devices

Angelov

Nikolov

Hristov

2019

Journal of Electrical and Computer Engineering

View full text Add to dashboard Cite

This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) new transistor architectures. Technology boosters such as high-k/metal-gate technologies, ultra-thin-body SOI, Ge-on-insulator (GOI), AIII–BV semiconductors, and band-engineered transistor (SiGe or Strained Si-channel) with high-carrier-mobility channels are examined. Nonclassical device structures such as novel multiple-gate transistor structures including multiple-gate field-effect transistors, FD-SOI MOSFETs, CNTFETs, and SETs are examined as possible successors of conventional CMOS devices and FinFETs. Special attention is devoted to gate-all-around FETs and, respectively, nanowire and nanosheet FETs as forthcoming mainstream replacements of FinFET. In view of that, compact modeling of bulk CMOS transistors and multiple-gate transistors are considered as well as BSIM and PSP multiple-gate models, FD-SOI MOSFETs, CNTFET, and SET modeling are reviewed.

show abstract

A practical Si nanowire technology with nanowire-on-insulator structure for beyond 10nm logic technologies

Cited by 26 publications

References 1 publication

Quantized Conduction and High Mobility in Selectively Grown In_xGa_1–xAs Nanowires

Quantized Conduction and High Mobility in Selectively Grown In_xGa_1–xAs Nanowires

Controlling the Wet-Etch Directionality in Nanostructured Silicon

Technology and Modeling of Nonclassical Transistor Devices

Contact Info

Product

Resources

About

A practical Si nanowire technology with nanowire-on-insulator structure for beyond 10nm logic technologies

Cited by 26 publications

References 1 publication

Quantized Conduction and High Mobility in Selectively Grown InxGa1–xAs Nanowires

Quantized Conduction and High Mobility in Selectively Grown InxGa1–xAs Nanowires

Controlling the Wet-Etch Directionality in Nanostructured Silicon

Technology and Modeling of Nonclassical Transistor Devices

Contact Info

Product

Resources

About

Quantized Conduction and High Mobility in Selectively Grown In_xGa_1–xAs Nanowires

Quantized Conduction and High Mobility in Selectively Grown In_xGa_1–xAs Nanowires