2016 IEEE International Electron Devices Meeting (IEDM) 2016
DOI: 10.1109/iedm.2016.7838496
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A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond

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Cited by 23 publications
(15 citation statements)
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“…The aggressive downscaling of CMOS transistors demands for design solutions to obtain large drive currents at small supply voltage and preserve low leakage currents. The possible options for technology improvement include the reduction of source/drain series resistance that is responsible for a degradation of the transistor on-current by 30%-40%, 1,2 the use of semiconductors alternative to silicon, [2][3][4][5][6][7][8] the introduction of stressors, 9,10 and the development of device architectures beyond planar FETs such as multi-gate FETs (MuGFETs). 7,9,11 In particular, for CMOS generations beyond the 7-nm node, gate-all-around (GAA) nanowire FETs appear to be the most promising architecture.…”
Section: Introductionmentioning
confidence: 99%
“…The aggressive downscaling of CMOS transistors demands for design solutions to obtain large drive currents at small supply voltage and preserve low leakage currents. The possible options for technology improvement include the reduction of source/drain series resistance that is responsible for a degradation of the transistor on-current by 30%-40%, 1,2 the use of semiconductors alternative to silicon, [2][3][4][5][6][7][8] the introduction of stressors, 9,10 and the development of device architectures beyond planar FETs such as multi-gate FETs (MuGFETs). 7,9,11 In particular, for CMOS generations beyond the 7-nm node, gate-all-around (GAA) nanowire FETs appear to be the most promising architecture.…”
Section: Introductionmentioning
confidence: 99%
“…After RCA cleaning, the gate stacks of SiO2/HZO/TiN were In the final step, the dopant is activated by using rapid thermal annealing (RTA) at 500°C for 30 secs in N2 ambient. A low Dit SiGe device can be produced by using common IL/HK/WFM gate stack [21]. Interface may be degraded as the Ge content increases; and Dit is related to the temperature during the following process.…”
Section: Device Fabricationmentioning
confidence: 99%
“…In addition, thermal budget management in a complex device structure is important to control the process window. In a typical replacement metal gate (RMG) flow of high-k/metal gate (HKMG) technologies, the contact anneal may come after the final gate stack formation [14], [15], where the MLA-induced epilayer regrowth has to be managed without damaging the gate and other surrounding functional modules. To that end, simulation is the only way of knowing distribution of heat sources in a device structure.…”
Section: Introductionmentioning
confidence: 99%