We fabricated the HfZrO 2 (HZO) ferroelectric fin field-effect transistors (Fe-FinFET) with fin width of 60 nm and gate length of 100 nm for ferroelectric nonvolatile memory operations. The fabricated Fe-FinFET exhibited a large memory window (MW) of 1.5 V and high (100 ns) program/erase speeds at ±5 V. After 10 5 program/erase cycles, the MW was maintained at 1.09 V and the retention time was measured up to 10 4 s with no degradation. The fabricated HZO Fe-FinFET is compatible with the current FinFET process and has a high MW, a fast program/erase speed, and excellent reliability. Therefore, the fabricated Fe-FinFET is a promising candidate for high-density ferroelectric field-effect transistor memory applications.

This paper reports a self-induced ferroelectric 2-nm-thick Ge-doped HfO2 (Ge:HfO2) thin film. Ge thermal desorption, incorporation into HfO2, and further Ge:HfO2 crystallization were all performed through rapid thermal annealing simultaneously. The ferroelectric property of a 2-nm-thick Ge:HfO2/2-nm-thick Al2O3 dielectric stack was confirmed using the polarization-electric field measurement. X-ray photoelectron spectroscopy was used to confirm that Ge bonded to HfO2 as Hf-germanates. Piezoresponse force microscopy was used to demonstrate the piezoelectric property of Ge:HfO2/Al2O3. Furthermore, a dielectric stack of Ge:HfO2/Al2O3 was applied as a gate insulator in a Ge nanowire gate-all-around ferroelectric field-effect transistor (Ge NW Fe-GAAFET). The device exhibited a minimum steep-sub-threshold slope of 47 mV/dec, a high ION/IOFF ratio of >106, and low gate leakage current; moreover, it was free of a drain-induced barrier lowering effect. The proposed self-induced ferroelectric Ge:HfO2 Ge NW Fe-GAAFET is feasible for future ultra-low power integrated circuit applications.

Present work demonstrates the vertically double stacked nanosheet (NS) p-channel polycrystalline silicon (poly-Si) junctionless field-effect transistors (JL-FET) with tri-gate, omega-gate, and gate all around (GAA) structure. These structures offer more W eff per existing footprint and better parallel resistance, resulting in smaller total resistance. Also, the GAA stacked NS device shows superior electrical properties, including high Ion/Ioff ratio (>10 8), steep subthreshold swing (SS) = 100 mV/dec, very low drain-induced-barrier-lowering (DIBL) = 0.127 mV/V and usually off at Vg = 0 V, owing to superior gate controllability. More, the 3D TCAD simulation has applied for analysis of physical characteristics of the proposed devices. INDEX TERMS Gate all around, junctionless, nanosheet, multi gate, stacked FET.

Ferroelectric fin field-effect transistors with a trench structure (trench Fe-FinFETs) were fabricated and characterized. The inclusion of the trench structures improved the electrical characteristics of the Fe-FinFETs. Moreover, short channel effects were suppressed by completely surrounding the trench channel with the gate electrodes. Compared with a conventional Fe-FinFET, the fabricated trench Fe-FinFET had a higher on–off current ratio of 4.1 × 107 and a steep minimum subthreshold swing of 35.4 mV/dec in the forward sweep. In addition, the fabricated trench Fe-FinFET had a very low drain-induced barrier lowering value of 4.47 mV/V and immunity to gate-induced drain leakage. Finally, a technology computer-aided design simulation was conducted to verify the experimental results.

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