This paper reports a self-induced ferroelectric 2-nm-thick Ge-doped HfO2 (Ge:HfO2) thin film. Ge thermal desorption, incorporation into HfO2, and further Ge:HfO2 crystallization were all performed through rapid thermal annealing simultaneously. The ferroelectric property of a 2-nm-thick Ge:HfO2/2-nm-thick Al2O3 dielectric stack was confirmed using the polarization-electric field measurement. X-ray photoelectron spectroscopy was used to confirm that Ge bonded to HfO2 as Hf-germanates. Piezoresponse force microscopy was used to demonstrate the piezoelectric property of Ge:HfO2/Al2O3. Furthermore, a dielectric stack of Ge:HfO2/Al2O3 was applied as a gate insulator in a Ge nanowire gate-all-around ferroelectric field-effect transistor (Ge NW Fe-GAAFET). The device exhibited a minimum steep-sub-threshold slope of 47 mV/dec, a high ION/IOFF ratio of >106, and low gate leakage current; moreover, it was free of a drain-induced barrier lowering effect. The proposed self-induced ferroelectric Ge:HfO2 Ge NW Fe-GAAFET is feasible for future ultra-low power integrated circuit applications.

Ferroelectric fin field-effect transistors with a trench structure (trench Fe-FinFETs) were fabricated and characterized. The inclusion of the trench structures improved the electrical characteristics of the Fe-FinFETs. Moreover, short channel effects were suppressed by completely surrounding the trench channel with the gate electrodes. Compared with a conventional Fe-FinFET, the fabricated trench Fe-FinFET had a higher on–off current ratio of 4.1 × 107 and a steep minimum subthreshold swing of 35.4 mV/dec in the forward sweep. In addition, the fabricated trench Fe-FinFET had a very low drain-induced barrier lowering value of 4.47 mV/V and immunity to gate-induced drain leakage. Finally, a technology computer-aided design simulation was conducted to verify the experimental results.

This study reports the ferroelectric (FE) layer of Hf0.5Zr0.5O2 (HZO) film on a Ge gate-all-around field-effect-transistor (GAAFET) with inversion mode (IM) and junctionless (JL) mode, and is the first that discuss the association of the JL field-effect transistor conduction mechanism in the subthreshold region with the transient negative capacitance (TNC) effect of the FE layer are discussed. The IM Ge FE-GAAFET exhibited a minimum subthreshold slope (SSmin) of 55 mV dec−1 and a high ION/IOFF ratio of >106. The sub-60 mV dec−1 SS result demonstrates surface potential amplification, which is attributed to the TNC effect. Furthermore, the Ge JL FE-GAAFETs exhibited an SSmin of 58 mV dec−1, a high ION/IOFF ratio (>105), and reverse drain-induced barrier lowering when compared with baseline HfO2 devices. These IM and JL Ge FE-GAAFETs are highly suitable for low-power integrated circuit applications.

This paper reports on the first unitary set of geometry-scalable, wide-hand compact models for all the components o f a 0.13 p m RF CMOS technology and which are valid up to 50 GHz. Verification of the active and passive device models i s achieved at the device level as well as by comparing measurements and simulation results of the S parameter response and jitter generation o f high-speed circuits operating above 10 GHz from a single 1.2-V supply.

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