We fabricated the HfZrO 2 (HZO) ferroelectric fin field-effect transistors (Fe-FinFET) with fin width of 60 nm and gate length of 100 nm for ferroelectric nonvolatile memory operations. The fabricated Fe-FinFET exhibited a large memory window (MW) of 1.5 V and high (100 ns) program/erase speeds at ±5 V. After 10 5 program/erase cycles, the MW was maintained at 1.09 V and the retention time was measured up to 10 4 s with no degradation. The fabricated HZO Fe-FinFET is compatible with the current FinFET process and has a high MW, a fast program/erase speed, and excellent reliability. Therefore, the fabricated Fe-FinFET is a promising candidate for high-density ferroelectric field-effect transistor memory applications.

Ferroelectric fin field-effect transistors with a trench structure (trench Fe-FinFETs) were fabricated and characterized. The inclusion of the trench structures improved the electrical characteristics of the Fe-FinFETs. Moreover, short channel effects were suppressed by completely surrounding the trench channel with the gate electrodes. Compared with a conventional Fe-FinFET, the fabricated trench Fe-FinFET had a higher on–off current ratio of 4.1 × 107 and a steep minimum subthreshold swing of 35.4 mV/dec in the forward sweep. In addition, the fabricated trench Fe-FinFET had a very low drain-induced barrier lowering value of 4.47 mV/V and immunity to gate-induced drain leakage. Finally, a technology computer-aided design simulation was conducted to verify the experimental results.

In this study, scaled ferroelectric fin field-effect transistors (Fe-FinFETs) based on HfZrO 2 were fabricated and characterized for multi-level cell (MLC) operations. With the scaled dimensions of 40 nm for the fin width and gate length of 200-320 nm, the fabricated Fe-FinFET exhibited a large memory window measuring 2.8 V, which is more fault-tolerant for MLC operations. Further, the Fe-FinFET depicted a high switching speed of 100 ns and clearly separated intermediate states, which are suitable for MLC operations. Robust endurance of up to 10 5 fatigue cycles for each state and a data retention time of up to 10 4 s without degradation were recorded. The Fe-FinFET demonstrates a high potential for high-density nonvolatile memory applications.

We have demonstrated the method of threshold voltage (VT) adjustment by controlling Ge content in the SiGe p-channel of N1 complementary field-effect transistor (CFET) for conquering the work function metal (WFM) filling issue on highly scaled MOSFET. Single WFM shared gate N1 CFET was used to study and emphasize the VT tunability of the proposed Ge content method. The result reveals that the Ge mole fraction influences VTP of 5 mV/Ge%, and a close result can also be obtained from the energy band configuration of Si1-xGex. Additionally, the single WFM shared gate N1 CFET inverter with VT adjusted by the Ge content method presents a well-designed voltage transfer curve, and its inverter transient response is also presented. Furthermore, the designed CFET inverter is used to construct a well-behaved 6T-SRAM with a large SNM of ~120 mV at VDD of 0.5 V.