A Minimum-Skew Clock Tree Synthesis Algorithm for Single Flux Quantum Logic Circuits

Shahsavani, Soheil Nazar; Pedram, Massoud

doi:10.1109/tasc.2019.2943930

Cited by 25 publications

(12 citation statements)

References 30 publications

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“…An SFQ clock network is significantly larger than a CMOS clock network due to the need for multiple splitters. Clock routing in SFQ systems is often performed with two approaches, global symmetric clock networks [55] followed by local asymmetric clock networks [19].…”

Section: Clock Tree Synthesis In Sfq Systemsmentioning

confidence: 99%

“…Local clock synthesis of SFQ circuits is used to produce a useful skew clock tree network within each block of the H-tree. A routing technique for asymmetric clock networks, based on the method of means and medians is proposed in [19] to minimize the skew within an SFQ clock tree. The location and number of clock sinks determine the topology of the clock tree network.…”

Section: Clock Tree Synthesis In Sfq Systemsmentioning

confidence: 99%

“…Novel area and power efficient splitters are needed to reduce this overhead while supporting large fanout. SFQ pulses propagate along a PTL at approximately one-third the speed of light without dissipation [19]. This feature motivates SFQ logic as a strong candidate for VLSI complexity ultra-high speed, ultra-low power digital applications.…”

mentioning

confidence: 99%

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Global interconnects in VLSI complexity single flux quantum systems

Jabbari

Friedman

2020

Proceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop

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Section: Clock Tree Synthesis In Sfq Systemsmentioning

confidence: 99%

Section: Clock Tree Synthesis In Sfq Systemsmentioning

confidence: 99%

See 1 more Smart Citation

Global interconnects in VLSI complexity single flux quantum systems

Jabbari

Friedman

2020

Proceedings of the Workshop on System-Level Interconnect: Problems and Pathfinding Workshop

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“…This is especially true when timing constraints are complex and combined with technology process variations, such as on-chip-variation (OCV) effects [1][2][3]. Additionally, a significant rise in the impact of uncertainties, such as process, voltage, or temperature variations [4], and the development of new applications, such as the Internet of Things, pose new challenges to IC design [5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Clock-Latency-Aware Pre-CTS for better Timing Closure in VLSI Design

Benallal¹,

Bouamama²,

Cherif³

et al. 2022

IJETAE

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A common strategy for reducing the time jump due to a clock tree insertion is to add a clock uncertainty value. If a small clock uncertainty value is selected for the Pre-CTS optimization, then a significant timing jump is observed when the clock tree is inserted, and clock timings are propagated. On the other hand, if the clock uncertainty is large, then the place and route (PNR) flow does not converge. This approach has been proven to be insufficient as each timing path is affected differently by the creation of the clock tree. In this paper, we suggest a more targeted approach whereby all pins in the clock tree will be annotated with their estimated latency, and therefore clock arrival times under ideal clocks should closely model the post-CTS arrival times. This objective is achieved by introducing an accurate and fast clock prediction early in the flow at the pre-CTS stage. As a result, the transition from the pre-CTS stage to the post-CTS stage becomes easier without significant timing jumps. An experiment on nine commercial test cases led to a significant TNS timing improvement of up to 68%, with an average of 35% at the end of the route stage. The full PNR flow runtime is not impacted. We achieved a 3% average runtime reduction over all test cases. Keywords—Clock-latency estimation, Clock-tree Synthesis, Integrated circuit conception, Physical implementation, Static timing analysis, Static timing closure.

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“…The approach considers both local and global timing uncertainties and effectively uses common path pessimism removal to reduce the number of inserted hold buffers on each timing path. (2) The placement of hold buffers is implemented by the qPlace tool [24] that is enhanced with an incremental placement strategy that generates high-quality solutions. (3) The approach is evaluated using dynamic timing analysis with a grid-based placement-aware variation model [28] on multiple ISCAS'85 benchmark circuits.…”

mentioning

confidence: 99%

A Variation-aware Hold Time Fixing Methodology for Single Flux Quantum Logic Circuits

Shahsavani

Zhou

et al. 2021

ACM Trans. Des. Autom. Electron. Syst.

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Single flux quantum (SFQ) logic is a promising technology to replace complementary metal-oxide-semiconductor logic for future exa-scale supercomputing but requires the development of reliable EDA tools that are tailored to the unique characteristics of SFQ circuits, including the need for active splitters to support fanout and clocked logic gates. This article is the first work to present a physical design methodology for inserting hold buffers in SFQ circuits. Our approach is variation-aware, uses common path pessimism removal and incremental placement to minimize the overhead of timing fixes, and can trade off layout area and timing yield. Compared to a previously proposed approach using fixed hold time margins, Monte Carlo simulations show that, averaging across 10 ISCAS’85 benchmark circuits, our proposed method can reduce the number of inserted hold buffers by 8.4% with a 6.2% improvement in timing yield and by 21.9% with a 1.7% improvement in timing yield.

show abstract

A Minimum-Skew Clock Tree Synthesis Algorithm for Single Flux Quantum Logic Circuits

Cited by 25 publications

References 30 publications

Global interconnects in VLSI complexity single flux quantum systems

Global interconnects in VLSI complexity single flux quantum systems

Clock-Latency-Aware Pre-CTS for better Timing Closure in VLSI Design

A Variation-aware Hold Time Fixing Methodology for Single Flux Quantum Logic Circuits

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